BiSuT: A NoC-Based Bit-Shuffling Technique for Multiple Permanent Faults Mitigation

Mercier, Romain; Killian, Cedric; Kritikakou, Angeliki; Helen, Youri; Chillet, Daniel

doi:10.1109/tcad.2021.3101406

Cited by 5 publications

(1 citation statement)

References 42 publications

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“…The post-fabrication test can be employed to find a set of locations of faults (due to manufacturing defects) in the SNN compute engine (i.e., fault map) at the design time (Zhang et al, 2018 ; Putra et al, 2021a ). Meanwhile, the online test strategy like the Built-In Self-Test (BIST) techniques can be employed to obtain the fault map (due to device wear out or physical damages) at the run time (Baloch et al, 2019 ; Wang et al, 2019 ; Mercier et al, 2022 ). Our RescueSNN methodology leverages this fault map to safely map the SNN weights and operations on the compute engine, thereby minimizing the negative impact of permanent faults .…”

Section: Rescuesnn Methodologymentioning

confidence: 99%

RescueSNN: enabling reliable executions on spiking neural network accelerators under permanent faults

2023

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To maximize the performance and energy efficiency of Spiking Neural Network (SNN) processing on resource-constrained embedded systems, specialized hardware accelerators/chips are employed. However, these SNN chips may suffer from permanent faults which can affect the functionality of weight memory and neuron behavior, thereby causing potentially significant accuracy degradation and system malfunctioning. Such permanent faults may come from manufacturing defects during the fabrication process, and/or from device/transistor damages (e.g., due to wear out) during the run-time operation. However, the impact of permanent faults in SNN chips and the respective mitigation techniques have not been thoroughly investigated yet. Toward this, we propose RescueSNN, a novel methodology to mitigate permanent faults in the compute engine of SNN chips without requiring additional retraining, thereby significantly cutting down the design time and retraining costs, while maintaining the throughput and quality. The key ideas of our RescueSNN methodology are (1) analyzing the characteristics of SNN under permanent faults; (2) leveraging this analysis to improve the SNN fault-tolerance through effective fault-aware mapping (FAM); and (3) devising lightweight hardware enhancements to support FAM. Our FAM technique leverages the fault map of SNN compute engine for (i) minimizing weight corruption when mapping weight bits on the faulty memory cells, and (ii) selectively employing faulty neurons that do not cause significant accuracy degradation to maintain accuracy and throughput, while considering the SNN operations and processing dataflow. The experimental results show that our RescueSNN improves accuracy by up to 80% while maintaining the throughput reduction below 25% in high fault rate (e.g., 0.5 of the potential fault locations), as compared to running SNNs on the faulty chip without mitigation. In this manner, the embedded systems that employ RescueSNN-enhanced chips can efficiently ensure reliable executions against permanent faults during their operational lifetime.

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Section: Rescuesnn Methodologymentioning

confidence: 99%

RescueSNN: enabling reliable executions on spiking neural network accelerators under permanent faults

2023

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ReNo: novel switch architecture for reliability improvement of NoCs

et al. 2022

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A Region-Based Bit-Shuffling Approach Trading Hardware Cost and Fault Mitigation Efficiency

Mercier

Killian

Kritikakou³

et al. 2021

2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

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Due to transistor shrinking and core number increasing in System-on-Chip (SoC), fault tolerance has become essential. Indeed, faults occurring to Network-on-Chips (NoCs) of those systems have a significant impact, due to the high amount of data crossing the NoC for communication. However, existing fault correction approaches cannot efficiently address several permanent faults on NoC, due to their high hardware costs. To mitigate the impact of faults, existing works shuffle the bits inside a flit, transferring the impact of faults on the least significant bits. However, such approaches are applied at a fine-grained level, providing fault mitigation efficiency but with significant hardware costs. To address this limitation, this work proposes a region-based bit-shuffling technique, applied at a coarse-grain level, that trades off fault mitigation efficiency in order to save hardware costs. The obtained results show that the area and power overheads can be reduced from 48% to 33% and from 34% to 22%, respectively, with a small impact on the Mean Square Error (MSE).

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BiSuT: A NoC-Based Bit-Shuffling Technique for Multiple Permanent Faults Mitigation

Cited by 5 publications

References 42 publications

RescueSNN: enabling reliable executions on spiking neural network accelerators under permanent faults

RescueSNN: enabling reliable executions on spiking neural network accelerators under permanent faults

ReNo: novel switch architecture for reliability improvement of NoCs

A Region-Based Bit-Shuffling Approach Trading Hardware Cost and Fault Mitigation Efficiency

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