BIST hardware synthesis for RTL data paths based on test compatibility classes

Abstract

New BIST methodology for RTL data paths is presented. The proposed BIST methodology takes advantage of the structural information of RTL data path and reduces the test application time by grouping same-type modules into test compatibility classes (TCCs). During testing, compatible modules share a small number of test pattern generators at the same test time leading to significant reductions in BIST area overhead, performance degradation and test application time. Module output responses from each TCC are checked by comparators leading to substantial reduction in fault-escape probability. Only a single signature analysis register is required to compress the responses of each TCC which leads to high reductions in volume of output data and overall test application time (the sum of test application time and shifting time required to shift out test responses). This paper shows how the proposed TCC grouping methodology is a general case of the traditional BIST embedding methodology for RTL data paths with both uniform and variable bit width. A new BIST hardware synthesis algorithm employs efficient tabu search-based testable design space exploration which combines the accuracy of incremental test scheduling algorithms and the exploration speed of test scheduling algorithms based on fixed test resource allocation. To illustrate TCC grouping methodology efficiency, various benchmark and complex hypothetical data paths have been evaluated and significant improvements over BIST embedding methodology are achieved.

An application-level synthesis methodology for multidimensional embedded processing systems

“…Candidate optimizing procedures are simulated annealing [42]- [44], genetic algorithms [41], [45], [46], and tabu search [23], [47], [48] (gradient-based algorithms cannot be applied, since we do not even require continuity for and ). All these direct techniques need to generate feasible candidate solutions and evaluate their fitness values .…”

Testability Trade-Offs for BIST Data Paths

“…In multiobjective optimization not a single optimal solution is targeted, but rather the Pareto set (Pareto curve) which is the set of all the feasible solutions whose vector of the multiple objectives is not dominated by the vector of any other solution. In the particular case of the two dimensional design space shown in Figure 6 Figure 6 justifies the need of efficient testable design space exploration algorithms, to consciously account for the interrelation between test synthesis and test scheduling [15,22]. However, trading-off only test application time and BIST area overhead will identify solutions belonging to the Pareto curve, which have high values in power dissipation.…”

“…However, the previous power-constrained test scheduling algorithms are based on fixed test resource allocation, and therefore have considered only the two dimensional trade-off between test application time and power dissipation. Further, it has been shown that test synthesis and test scheduling are strictly interrelated [15,22] justifying that fixed test resource formulation leads to inefficient exploration of the testable design space. So far, the interrelation between test synthesis and test scheduling has considered only the two dimensional trade-off between test application time and BIST area overhead.…”

Integrating self testability with design space exploration by a controller based estimation technique

“…Automatic insertion of BIST into RTL data-path description has been the subject of intensive research over the last few years with considerable success [4,6,7,9]. But the approaches have addressed different levels of abstraction.…”

“…But the approaches have addressed different levels of abstraction. The approaches of [4,7] addressed the testability optimisation at the zone III of Figure 1, while the methods published by [6,7] operated on zones II and III. Other published works like that of [8] gave constructive approaches.…”