VLSI Circuits and Systems V 2011
DOI: 10.1117/12.887123
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Bio-inspired FPGA architecture for self-calibration of an image compression core based on wavelet transforms in embedded systems

Abstract: A generic bio-inspired adaptive architecture for image compression suitable to be implemented in embedded systems is presented. The architecture allows the system to be tuned during its calibration phase. An evolutionary algorithm is responsible of making the system evolve towards the required performance. A prototype has been implemented in a Xilinx Virtex-5 FPGA featuring an adaptive wavelet transform core directed at improving image compression for specific types of images.An Evolution Strategy has been cho… Show more

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Cited by 2 publications
(12 citation statements)
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References 21 publications
(15 reference statements)
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“…However, compressed image have been still scaled (here, scale has the same meaning than DWT level or decimation process) by 2 or even by 4, in order to get 128x128pels or 64x64pels images respectively and to be able to compare these results although there is not a noticeable improvement. In those cases the PSNR decreases even to 22,50dB which are yet comparable to the results obtained in [13] and [14]. In all those experiments a very simple interpolation algorithm has been employed for recovering the original image size, based on the duplication of the neighbor pel.…”
Section: (4)supporting
confidence: 73%
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“…However, compressed image have been still scaled (here, scale has the same meaning than DWT level or decimation process) by 2 or even by 4, in order to get 128x128pels or 64x64pels images respectively and to be able to compare these results although there is not a noticeable improvement. In those cases the PSNR decreases even to 22,50dB which are yet comparable to the results obtained in [13] and [14]. In all those experiments a very simple interpolation algorithm has been employed for recovering the original image size, based on the duplication of the neighbor pel.…”
Section: (4)supporting
confidence: 73%
“…The prototype platform used in [13] and [14] however is an ML507 development board, which contains a Xilinx Virtex 5 (XCVFX70T) FPGA device with an embedded PowerPC processor, responsible of running the Evolutionary Algorithm described. In that implementation, one result is obtained each two cycles, so the computation time of the whole wavelet at 150MHz clock cycle is 0,873msec.…”
Section: Fpga Implementation Resultsmentioning
confidence: 99%
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