2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)
DOI: 10.1109/iscas.2002.1010778
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Bio-inspired analog parallel array processor chip with programmable spatio-temporal dynamics

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Cited by 6 publications
(6 citation statements)
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“…The prototype chip has been designed and fabricated in a 0.5 single-poly triple-metal CMOS technology [38]. Its dimensions are 9.27 8.45 sq.…”
Section: B Prototype Chip Datamentioning
confidence: 99%
“…The prototype chip has been designed and fabricated in a 0.5 single-poly triple-metal CMOS technology [38]. Its dimensions are 9.27 8.45 sq.…”
Section: B Prototype Chip Datamentioning
confidence: 99%
“…The sources are connected through capacitors to ground. We assume all transistors operate in weak inversion and are saturated, so the drain currents representing the layer are given by (9) where and are the gate and source voltages referenced to the bulk node. Differentiating with respect to time (10) where is the current entering the capacitor C. To implement the network, we equate the current flowing out of the capacitor with the sum on the right hand side of the element-wise product operator in (3).…”
Section: A Implementation Of State Variablesmentioning
confidence: 99%
“…A recent CMOS implementation of the circuit architecture in [6] contains six second-order cells [8]. One notable exception is the 32 32 cell two-layer cellular neural network (CNN) architecture described by Carmona et al [9]. The chip we report here differs from that chip in that it represents signals differentially and is implemented using transistors operating in weak, rather than strong, inversion.…”
Section: Introductionmentioning
confidence: 99%
“…Many artificial, physical, chemical, as well as biological systems have been represented by Cellular Neural Networks (CNN) models [16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31]. Its continuous-time analog operation allows real-time signal processing at high precision, while its local interaction between the constituent Processing Elements (PEs) obviate the need of global buses and long interconnects, leading to several digital and analog implementations of CNN architectures in the form of Very Large-Scale Integrated (VLSI) chips.…”
Section: Introductionmentioning
confidence: 99%