Bilateral Testing of Nano-scale Fault-tolerant Circuits

Fang, Lei; Hsiao, Michael S.

doi:10.1109/dft.2006.17

Cited by 5 publications

(3 citation statements)

References 23 publications

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“…faults that appear during the normal functioning of the system, irrespective of their transient or permanent nature [2]. Moreover, it has been shown in [3,4,5] that they could also tolerate permanent defects and thus help improving the manufacturing yield.…”

Section: Introductionmentioning

confidence: 99%

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A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits

Tran

Virazel

Bosio

et al. 2011

2011 Asian Test Symposium

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In this paper, a novel hybrid fault tolerant architecture for digital circuits is proposed in order to enable the use of future CMOS technology nodes. This architecture targets robustness, power consumption and yield at the same time, at area costs comparable to standard fault tolerance schemes. The architecture increases circuit robustness by tolerating both transient and permanent online faults. It consumes less power than the classical Triple Modular Redundancy (TMR) approach while utilizing comparable silicon area. It overcomes many permanent faults occurring throughout manufacturing while still tolerating soft errors introduced by particle strikes. These can be done by using scalable redundancy resources, while keeping the hardened combinational logic circuits intact. The technique combines different types of redundancy: information redundancy for error detection, temporal redundancy for soft error correction and hardware redundancy for hard error tolerance. Results on largest ISCAS and ITC benchmark circuits show that our approach has an area cost negligible of about 2% to 3% with a power consumption saving of about 30% compared to TMR. Finally, it deals with aging phenomenon and thus, increases the expected lifetime of logic circuits.

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Section: Introductionmentioning

confidence: 99%

“…While increasing fault tolerance capability, keeping a low area overhead is also a main optimization criterion of these works. In [3,4,5], the authors proposed manufacturing yield improvement as a new goal. Beside, other aspects such as power consumption, aging and expected lifetime of circuits are of the same importance.…”

Section: Introductionmentioning

confidence: 99%

A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits

Tran

Virazel

Bosio

et al. 2011

2011 Asian Test Symposium

View full text Add to dashboard Cite

show abstract

“…faults that appear during normal system operations, irrespective of their transient of permanent nature [2]. However, it has been shown in [3,4,5] that these architectures could also tolerate permanent defects and hence, improve the manufacturing yield.…”

mentioning

confidence: 99%

A pseudo-dynamic comparator for error detection in fault tolerant architectures

Tran

Virazel

Bosio

et al. 2012

2012 IEEE 30th VLSI Test Symposium (VTS)

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Although CMOS technology scaling offers many advantages, it suffers from robustness problem caused by hard, soft and timing errors. The robustness of future CMOS technology nodes must be improved and the use of fault tolerant architectures is probably the most viable solution. In this context, Duplication/Comparison scheme is widely used for error detection. Traditionally, this scheme uses a static comparator structure that detects hard error. However, it is not effective for soft and timing errors detection due to the possible masking of glitches by the comparator itself. To solve this problem, we propose a pseudo-dynamic comparator architecture that combines a dynamic CMOS transition detector and a static comparator. Experimental results show that the proposed comparator detects not only hard errors but also small glitches related to soft and timing errors. Moreover, its dynamic characteristics allow reducing the power consumption while keeping an equivalent silicon area compared to a static comparator. This study is the first step towards a full fault tolerant approach targeting robustness improvement of CMOS logic circuits.

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