Bidwidth analysis with application to silicon compilation

Abstract

This paper introduces Bitwise, a compiler that minimizes the bitwidth | the number of bits used to represent e a c h operand | for both integers and pointers in a program. By propagating static information both forward and backward in the program data ow g r a p h , B i t wise frees the programmer from declaring bitwidth invariants in cases where the compiler can determine bitwidths automatically. Because loop instructions comprise the bulk of dynamically executed instructions, Bitwise incorporates sophisticated loop analysis techniques for identifying bitwidths. We n d a r i c h o pportunity for bitwidth reduction in modern multimedia and streaming application workloads. For new architectures that support sub-word data-types, we expect that our bitwidth reductions will save power and increase processor performance.This paper also applies our analysis to silicon compilation, the translation of programs into custom hardware, to realize the full bene ts of bitwidth reduction. We describe our integration of Bitwise with the DeepC Silicon Compiler. By taking advantage of bitwidth information during architectural synthesis, we reduce silicon real estate by 15 { 86%, improve clock speed by 3 { 249%, and reduce power by 46 { 73%. The next era of general purpose and recon gurable architectures should strive to capture a portion of these gains.

Reconciling specialization and flexibility through compound circuits

“…Also more aggressive circuit exploration and matching can be investigated to achieve more space/time tradeoffs, for instance, matching an existing barrel shifter or a simple adder to a multiply-by-two operator. Our approach can also greatly benefit from bit-width analysis [25] and progressive decomposition techniques [26] to optimize the arithmetic operators of compound circuits.…”

Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure

“…Techniques based on the value range analysis were extensively used in high-level code transformations [35,36,37]. In [28], the information about the operand sizes was used to rewrite the source code such that each data type has an associated width component.…”

Wordlength optimization for linear digital signal processing

“…Some published approaches to the wordlength optimization problem use an analytic approach to scaling and/or error estimation [5], [7], [9], some use simulation [6], [8], and some use a hybrid of the two [10]. The advantage of analytic techniques is that they do not require representative simulation stimulus, and can be faster, however, they tend to be more pessimistic.…”

“…The advantage of analytic techniques is that they do not require representative simulation stimulus, and can be faster, however, they tend to be more pessimistic. There is little analytical work on supporting dataflow graphs containing cycles, although in [9], finite loop bounds are supported. Some published approaches use worst-case instantaneous error as a measure of signal quality [5], [7], [8] whereas some use signal-to-noise ratio (SNR) [1], [6].…”

“…The Bitwise Project [9] proposes propagation of integer variable ranges backward and forward through dataflow graphs. The focus is on removing unwanted most-significant bits (MSBs).…”