Bias Temperature Instability analysis of FinFET based SRAM cells

Khan, Shahzad; Agbo, Innocent; Hamdioui, Said; Kükner, Halil; Kaczer, B.; Raghavan, Praveen; Catthoor, Francky

doi:10.7873/date.2014.044

Cited by 13 publications

(19 citation statements)

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“…Atomistic model is based on the assumption that during the manufacturing of the chip, the chip has a latent defects on it which is only activated when the chip is stressed or charged, resulting into an activated traps. These traps are function of temperature, supply voltage, duty factor, and workloads [67,73,74,[79][80][81][82][83][84][85][86][87][88][89][90][91][92].…”

Section: Temporal/aging Variationsmentioning

confidence: 99%

“…Hu et al investigated in [139] the integral impact of both process variation and temporal degradation for FinFET technology while taking into account various memory cell arrays. Khan et al analyzed in [140] a comprehensive aging degradation based on FinFET memory cell while considering various supply voltages, cell strength, designs, and technologies.…”

Section: Sismentioning

confidence: 99%

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Reliability Modeling and Mitigation for Embedded Memories

Agbo

Taouil

Hamdioui

2019

2019 IEEE International Test Conference (ITC)

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Complementary Metallic Oxide Semiconductor (CMOS) technology scaling enhances the performance, transistor density, functionality, and reduces cost and power consumption. However, scaling causes significant reliability challenges both from a manufacturing and operational point of view. Obtaining reliable memories require accurate understanding of the impact of aging (such as Bias temperature instability (BTI)) on individual memory components and how they interact with each other. In this dissertation, two types of challenges are addressed, which are related to BTI aging and partially to mitigation schemes: one related to the aging of sense amplifier and another one to the aging of read path and write path. Analysis of aging impact on different memory sense amplifiers-The analysis of BTI impact on various memory sense amplifier (SA) designs was performed, while taking into account two BTI models (i.e., Atomistic and RD model), different technology nodes (i.e., 90, 65, 45, 32, 22, and 16 nm), and different workloads. First, the analysis and comparison of RD and Atomistic models impact on the SA were performed. The results show that the atomistic trap-based BTI model is more accurate than the RD model. Second, the investigation of BTI impact on the drain-input latch type SA for various technology nodes and supply voltages was performed. The result shows that as technology scales down, the impact of BTI on sensing delay increases, while the sensing voltage decreases, causing less robust and reliable memory sense amplifier. The result also shows that increase in supply voltage compensates the BTI degradation. Third, an accurate technique was proposed and characterized for the integral impact of BTI and voltage temperature variation on the memory standard latch type SA for various technology nodes and workloads. The results show that the degradation is strongly dependent on workload and temperature. Fourth, in addition to the latter, the impact of process variation at timezero was incorporated and analyzed. The results show that the SA sensing delay degradation is more significant at lower nodes and could lead to read failures at lower power supply. This reveals that there must be a tradeoff between performance and reliability. Fifth, an accurate methodology was proposed to quantify the impact of variability on the memory SA offset-voltage for both time-zero and time-dependent variability. The results show that the impact on the offset voltage specification is significant for aging time-dependent variability. Sixth, on top of the latter, the sensitivity of the SA and its failure rate were analyzed for five process corners (i.e., Nominal, Fast-Fast, Fast-Slow, Slow-Fast, and Slow-Slow). The results show that balanced workloads result in a significant low offset voltage specification. Finally, the impact of aging was analyzed and compared, while considering different supply voltages, temperatures, and SA designs. The results show that the High Performance SA degrades faster than other SA types, irrespective of the workloa...

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Section: Temporal/aging Variationsmentioning

confidence: 99%

Section: Sismentioning

confidence: 99%

Reliability Modeling and Mitigation for Embedded Memories

Agbo

Taouil

Hamdioui

2019

2019 IEEE International Test Conference (ITC)

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“…This operating condition stands true for any SRAM cell as whatever the stored data; one of its PMOS will be undergoing an NBTI stress. Moreover, CMOS SRAM continues to be the technology of choice for cache memory despite the progressive introduction of new emerging memory technologies [1], As such, with technology scaling, NBTI will continue to be the main reliability challenge for current and future generation of SRAMs [3][4][5][6]. Thus, ageing-aware design techniques that alleviate NBTI have to be introduced to ensure reliable systems embedding them.…”

Section: Introductionmentioning

confidence: 99%

Sizing of the CMOS 6T‐SRAM cell for NBTI ageing mitigation

Chenouf

Djezzar

Bentarzi

et al. 2020

IET Circuits, Devices & Systems

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This study presents a negative bias temperature instability (NBTI) mitigation design technique for CMOS 6T-static random access memory (6T-SRAM) cells. The proposed approach is based on transistor sizing technique. It consists of sizing the nMOS access transistors of the cell to alleviate NBTI ageing occurring in its pMOS pull-up transistors threatening the cell stability. Once the access transistors are sized for a better hold static noise margin under NBTI, the other transistors of the 6T-SRAM cell could be properly sized for improved read stability and write-ability.

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“…Previous works have mainly focused on estimating and mitigating the impact of aging on the memory cell array [6][7][8][9][10]. Most of these works aim at balancing the probability of writing zeroes and ones to the memory cells, as this minimizes their degradation.…”

Section: Introductionmentioning

confidence: 99%

Hardware-Based Aging Mitigation Scheme for Memory Address Decoder

Kraak

Agbo

Taouil

et al. 2019

2019 IEEE European Test Symposium (ETS)

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Designers typically add design margins to memories to compensate for their aging. As the aging impact increases with technology scaling, bigger margins become necessary. However, this negatively impacts area, yield, performance, and power consumption. Alternatively, mitigation schemes can be used to reduce the impact of aging. This paper proposes a hardwarebased mitigation scheme for the memory's address decoder logic. The scheme is based on adapting the decoder's workload during idle cycles by stressing the short paths and putting long paths into relaxation. Thanks to the adapted workload, the impact of aging on the address decoder is reduced, resulting in a more reliable memory. To validate the benefit of the mitigation scheme, the decoder's degradation of the L1 data and instruction caches for an ARM v8-a processor is analyzed. The experimental results show that the proposed mitigation scheme reduces the degradation of the decoder's timing margin with up to 4.1x at negligible area and no more than 3% power overhead.

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Bias Temperature Instability analysis of FinFET based SRAM cells

Cited by 13 publications

References 0 publications

Reliability Modeling and Mitigation for Embedded Memories

Reliability Modeling and Mitigation for Embedded Memories

Sizing of the CMOS 6T‐SRAM cell for NBTI ageing mitigation

Hardware-Based Aging Mitigation Scheme for Memory Address Decoder

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