Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS Architectures

Panades, Ivan Miro; Greiner, Alain

doi:10.1109/nocs.2007.14

Cited by 92 publications

(57 citation statements)

References 21 publications

(31 reference statements)

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“…The advantage of FIFO is that they do not affect the locally synchronous domain"s operation. Many FIFO based designs have been published recently [5], [6] and [7].…”

Section: A Fifo Solutionmentioning

confidence: 99%

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Design of a Self-Timed Data Synchronizer for Crossing Two Different Clock Domains

Zakaria¹,

Nawar²

2017

IJCA

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This paper presents asynchronous switch between any two different local clock synchronous domains. The asynchronous switch will generate a slower clock from two local clock modules and moderate the high rated clock domain to slow down its clock frequency without stopping or pausing any clock of them throughout the data communication among them. The proposed design is implemented using the CMOS 45nm technology of STMicroelectronics. In this case, the delay time to change the clock is shown to be about 0.4ns. The proposed system is designed to use a small number of circuit elements. Sothat, the asynchronous switch has a noticeable improvement in terms of power consumption, throughput, and circuit area.

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“…The advantage of FIFO is that they do not affect the locally synchronous domain"s operation. Many FIFO based designs have been published recently [5], [6] and [7].…”

Section: A Fifo Solutionmentioning

confidence: 99%

“…The asynchronous switch is designed to manage the connection of Ring-out-Req and Ring-out-Ack signals with the handshaking Req-ANOC and Ack-ANOC signals as depicted in figure (6). If com signal equals 1(i.e.…”

Section: Asynchronous Switchmentioning

confidence: 99%

Design of a Self-Timed Data Synchronizer for Crossing Two Different Clock Domains

Zakaria¹,

Nawar²

2017

IJCA

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“…The final DVFS accurately models timing aspects as well as worst power consumption. The GALS support implements two resynchronization schemes, handshake [17] and FIFO [18], allowing trading area and power consumption over performance penalties. Both the handshake and the FIFO resynchronizers allows to partition the design into multiple VFIs, even if the handshake one severely impacts the system performance, as discussed in Section 3.5 and Section 4.4.…”

Section: Novel Contributionmentioning

confidence: 99%

“…The busy signal is used to prevent the transmission of new flits until the reception of the acknowledge signal. FIFO Resynchronizer Starting from the work in [18], the proposed framework implements the FIFO model to resynchronize two routers as well as its connected computational and memory components. The FIFO resynchronizer allows to decouple the transmitter and receiver, since the former can send data up to fully fill the FIFO at its own frequency while the receiver can read data up to the frequency of the sender.…”

Section: Handshake Resynchronizermentioning

confidence: 99%

A DVFS Cycle Accurate Simulation Framework with Asynchronous NoC Design for Power-Performance Optimizations

Zoni

Terraneo

Fornaciari

2015

J Sign Process Syst

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Network-on-Chip (NoC) is a flexible and scalable solution to interconnect multi-cores, with a strong influence on the performance of the whole chip. On-chip network affects also the overall power consumption, thus requiring accurate early-stage estimation and optimization methodologies. In this scenario, the Dynamic Voltage Frequency Scaling (DVFS) technique have been proposed both for CPUs and NoCs. The promise is to be a flexible and scalable way to jointly optimize power-performance, addressing both static and dynamic power sources. Being simulation a de-facto prime solution to explore novel multi-core architectures, a reliable full system analysis requires to integrate in the toolchain accurate timing and power models for the DVFS block and for the resynchronization logic between different Voltage and Frequency Islands (VFIs). In such a way, a more accurate validation of novel optimization methodologies which exploit such actuator is possible, since both architectural and actuator overheads are considered at the same time. This work proposes a complete cycle accurate framework for multi-core design supporting Global Asynchronous Local Synchronous (GALS) NoC design and DVFS actuators for the NoC. Furthermore, static and dynamic frequency assignment is possible with or without the use of the voltage regulator. The proposed framework sits on accurate analytical timing model and

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“… FIFO buffers: using asynchronous FIFO buffers between locally synchronous blocks to hide the synchronization problem. This technique can be seen in various NoC designs as [97,98].  Boundary synchronization: performing boundary synchronization on the signals crossing the borders of the locally synchronous island without stopping the complete locally synchronous block during data transfer [94].…”

Section: A Asynchronous Processorsmentioning

confidence: 99%

Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review

Qadri¹,

Gujarathi²,

McDonald-Maier³

2009

JCP

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Abstract-The technological evolution has increased the number of transistors for a given die area significantly and increased the switching speed from few MHz to GHz range. Such inversely proportional decline in size and boost in performance consequently demands shrinking of supply voltage and effective power dissipation in chips with millions of transistors. This has triggered substantial amount of research in power reduction techniques into almost every aspect of the chip and particularly the processor cores contained in the chip. This paper presents an overview of techniques for achieving the power efficiency mainly at the processor core level but also visits related domains such as buses and memories. There are various processor parameters and features such as supply voltage, clock frequency, cache and pipelining which can be optimized to reduce the power consumption of the processor. This paper discusses various ways in which these parameters can be optimized. Also, emerging power efficient processor architectures are overviewed and research activities are discussed which should help reader identify how these factors in a processor contribute to power consumption. Some of these concepts have been already established whereas others are still active research areas.

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Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS Architectures

Cited by 92 publications

References 21 publications

Design of a Self-Timed Data Synchronizer for Crossing Two Different Clock Domains

Design of a Self-Timed Data Synchronizer for Crossing Two Different Clock Domains

A DVFS Cycle Accurate Simulation Framework with Asynchronous NoC Design for Power-Performance Optimizations

Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review

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