Beyond Moore's law – A critical review of advancements in negative capacitance field effect transistors: A revolution in next-generation electronics

Valasa, Sresta; Kotha, Venkata Ramakrishna; Vadthiya, Narendar

doi:10.1016/j.mssp.2024.108116

Cited by 3 publications

(2 citation statements)

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“…Although the debut of FinFETs at the 22 nm node provided advancements in gate control and the mitigation of short channel effects (SCEs) at lower channel lengths, yet when these devices are downscaled to sub-10 nm channel lengths, a continuous set of challenges emerged that include elevated SCEs, increased SS, etc. 7,8 Moreover, in the realm of advanced semiconductor nodes, specifically in the 3 nm and beyond, the ongoing downscaling in contact and fin pitches posed a considerable challenge.…”

Section: Introductionmentioning

confidence: 99%

“…Furthermore, the state-of-the-art FinFET technology is being replaced by gate all around (GAA) technology rapidly in the past five years. Although the debut of FinFETs at the 22 nm node provided advancements in gate control and the mitigation of short channel effects (SCEs) at lower channel lengths, yet when these devices are downscaled to sub-10 nm channel lengths, a continuous set of challenges emerged that include elevated SCEs, increased SS, etc. , Moreover, in the realm of advanced semiconductor nodes, specifically in the 3 nm and beyond, the ongoing downscaling in contact and fin pitches posed a considerable challenge. Attempting to accommodate two or more fins within a standard cell configuration amplifies the complexities associated with fabrication.…”

Section: Introductionmentioning

confidence: 99%

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Pushing the Boundaries: Design and Simulation Approach of Negative Capacitance Nanosheet FETs with Ferroelectric and Dielectric Spacers at the Sub-3 nm Technology Node for Analog/RF/Mixed Signal Applications

Valasa,

Kotha,

Vadthiya

2024

ACS Appl. Electron. Mater.

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This manuscript for the first time introduces an approach of incorporating ferroelectric (FE) spacers in the negative capacitance (NC) nanosheet (NS) field-effect transistor (FET) instead of dielectric (DE) spacers in the source/drain extension region, specifically targeting sub-3 nm technology nodes. Four configurations are proposed for the examination: Both DE, Both FE, Drain-FE Source-DE, and Source-FE Drain-DE that address the need for improved performance and proper spacer material selection. The analysis starting from device level (digital/analog/radio frequency) to circuit (CMOS inverter) as a whole package is investigated through well-calibrated TCAD simulation, and the results portrayed Source-FE Drain-DE spacer placement as the best configuration in all aspects. Through digital performance evaluation, it has been found that the I on/I off ratio improves by an amount of ∼54.96%, ∼ 39.01%, and ∼37.61% for Both FE, Drain-FE Source-DE, and Source-FE Drain-DE spacers, respectively, as compared to Both DE spacers. An insight into eradication of negative differential resistance (NDR) and reduction of the subthreshold slope is also presented through proper placement of spacer material. All the analog/RF figure of merits (FOMs) such as g m, A V, f T, f max, , gfp, tfp, and gtfp are enhanced for the Source-FE Drain-DE configuration by an amount of ∼13.4%, ∼24%, ∼70.38%, ∼41.05%, ∼43.21%, ∼ 60.89%, and ∼60.47%, respectively, as compared to the Both DE configuration. We also assessed a design space window to achieve favorable capacitance matching, aiming for the NC effect in the pursuit of an optimized device design. Moreover, the CMOS inverter (layout is also designed) and CS amplifier circuits for all the four proposed configurations are examined and it is found that Source-FE Drain-DE gives better inverter performance with a reduced delay and PDP of ∼4.38 ps and ∼26.7 aJ as compared with other configurations. Overall, this work contributes to the scientific understanding of NC-NSFETs and spacer engineering, highlighting the potential of FE materials in advancing semiconductor technologies and paving the way for future innovations in digital, analog/RF, and mixed signal applications.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%