Beyond Fat--tree: Unidirectional Load--Balanced Multistage Interconnection Network

Gómez, C.; Gilabert, Francisco Jurado; Gómez, María E.; López, Pedro; Duato, J.

doi:10.1109/l-ca.2008.8

Cited by 15 publications

(9 citation statements)

References 14 publications

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“…Otherwise, it is noteworthy that this calculation was made over the computation in order of some ms. Compared to previous studies [28,52], the proposed method enables to estimate the attenuations and delays in function of level numbers which can be in order of hundreds.…”

Section: Investigation On More Than 10 Levels T-tree Structurementioning

confidence: 99%

“…So, intensive researches were performed on the modeling of the interconnect networks in order to predict the signal integrity (SI) [9,[11][12][13][14][15][17][18][19][20][21][22][23][24]. To minimize the cost and energy consumption and also for sharing data and clock signals through multipath circuits can be composed of ICs packaged in different levels this later is fundamental [25][26][27][28]. In this optic, different topologies as a typical H-tree interconnect [17,25] were investigated.…”

Section: Introductionmentioning

confidence: 99%

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Behavioral Model of Symmetrical Multi-Level T-Tree Interconnects

Ravelo¹

2012

PIER B

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Abstract-An accurate and behavioral modeling method of symmetrical T-tree interconnect network is successfully investigated in this paper. The T-tree network topology understudy is consisted of elementary lumped L-cells formed by series impedance and parallel admittance. It is demonstrated how the input-output signal paths of this single input multiple output (SIMO) tree network can be reduced to single input single output (SISO) network composed of L-cells in cascade. The literal expressions of the currents, the input impedances and the voltage transfer function of the T-tree electrical interconnect via elementary transfer matrix products are determined. Thus, the exact expression of the multi-level behavioral T-tree transfer function is established. The routine algorithm developed was implemented in Matlab programs. As application of the developed modeling method, the analysis of T-tree topology comprised of different and identical RLC-cells is conducted. To demonstrate the relevance of the model established, lumped RLC T-tree networks with different levels for the microelectronic interconnect application are designed and simulated. The work flow illustrating the guideline for the application of the routine algorithm summarizing the modeling method is proposed. Then, 3D-microstrip T-tree interconnects with width 0.1 µm and length 3 mm printed on FR4-substrate were considered. As results, a very good agreement between the results from the reduced behavioral model proposed and SPICE-computations is found both in frequency-and timedomains by considering arbitrary binary sequence "01001100" with 2 Gsym/s rate. The model proposed in this paper presents significant benefits in terms of flexibility and very less computation times. It can be used during the design process of the PCB and the microelectronic circuits for the signal integrity prediction. In the continuation of this 24Ravelo work, the modeling of clock T-tree interconnects for packaging systems composed of distributed elements using an analogue process is in progress.

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Section: Investigation On More Than 10 Levels T-tree Structurementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Behavioral Model of Symmetrical Multi-Level T-Tree Interconnects

Ravelo¹

2012

PIER B

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“…Additionally, this effect is more noticeable when combining topologies with more than two dimensions with an increment in the number of cores per switch. On the other hand, the use of fat-trees, combined with the appropriate routing algorithms, provide better performance for medium and large size NoCs [15]. Regarding routing in NoCs, SARC provides efficient and compact implementations of routing algorithms, like the Logic-Based Distributed Routing (LBDR) [16].…”

Section: Network-on-chip Architecturementioning

confidence: 99%

Explicit Communication and Synchronization in SARC

et al. 2010

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SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible occurrence of events that may trigger responses like coherence actions, RDMA, synchronization, or configurable event notifications. The fully virtualized and protected user-level API is based on specially marked lines in the scratchpad space that respond as command buffers, counters, or queues. The runtime system maps communication abstractions of the programming model to data transfers among local memories using remote write or read DMA and into task synchronization and scheduling using notifications, counters, and queues. The on-chip network provides efficient communication among these configurable memories, using advanced topologies and routing algorithms, and providing for process variability in NoC links. We simulate benchmark kernels on a full-system simulator to compare speedup and network traffic against cache-only systems with directory-based coherence and prefetchers. Explicit communication provides 10 to 40% higher speedup on 64 cores, and reduces network traffic by factors of 2 to 4, thus economizing on energy and power; lock and barrier latency is reduced by factors of 3 to 5. EXPLICIT COMMUNICATION AND NETWORK INTERFACE EVOLUTIONInterprocessor communication (IPC) is the basis of parallel processing. IPC can be implicit, when the addresses supplied by the software do not identify physical data locations or (time of) movement, or it can be explicit, when software (the application, or compiler, or runtime system) is able to also indicate physical placement or transfers, besides specifying computation on data. The SARC architecture [1], supports both implicit IPC, through cache coherence, for ease of programming, and explicit IPC, through scratchpad memories and remote store instructions or remote DMA operations, to be used by software whenever possible for achieving scalable performance.In order to hide IPC latency, when using implicit communication, we need large issue windows in out-of-order-execution processors, or sophisticated data prefetchers, or both. Explicit communication has the potential to better hide IPC latency, in those cases when software knows better than hardware what transfers need to take place and when. Remote store instructions, to addresses that indicate proximity to the consumer, when that is known at production time, will transfer data at the earliest possible time; hardware should coalesce writes to adjacent targets into few network packets, and the processor should not wait for the arrival acknowledgments. Remote direct memory access (RDMA) is the other method for explicit communication, in cases that require either reads -when the consumer is unknown or unavailable at production time-or multi-word writes -to achieve good coalescence.Traditional systems viewed networks as external (slow) devices, provided DMA in the network interface (NI), and interacted to it through (slow) input/output (I...

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“…Fat-tree networks [9] (and many variants of them) have been widely used in the field of Network-on-Chip (NoC) [12], [4], [3], [8], [11]. As suggested by its name, a fat-tree network is constructed from a tree, where each node in the tree is a switch and each leaf is an input/ouput port.…”

Section: Introductionmentioning

confidence: 99%

“…There are several existing approaches for coping with the scalability issue of fat-tree networks. Most of them require changing the tree topology and adding buffers in nodes, e.g., generalized fat trees [12], Dragonfly [8], and Unidirectional Load-Balanced Multistage Interconnection Networks [3]. In this paper, we adopt a different approach that can still maintain the original tree topology without adding any buffers in internal nodes.…”

Section: Introductionmentioning

confidence: 99%

Load-balanced Birkhoff-von Neumann switches and fat-tree networks

Chueh

Lien

Chang

et al. 2013

2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR)

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Abstract-Fat-tree networks have been widely used in the field of Network-on-Chip. One of the key issues in a fat-tree network is that the degree of a node has to be increased rapidly from the bottom of the tree to the root. As such, the complexity of implementing the switches near the root could be extremely high, and this poses a serious scalability issue. To cope with the scalability issue in fat-tree networks, many previous works require changing the tree topology and adding buffers in nodes. Unlike the existing arts, we adopt a different approach that can still maintain the original tree topology without adding any buffers in internal nodes. Our key idea is to explore various nice features of the load-balanced Birkhoff-von Neumann switches. Such switches have been shown to achieve 100% throughput for all admissible traffic and have comparable delay performance to the ideal output-buffered switch when traffic is heavy and bursty. We show that the implementation complexity can be greatly reduced if a fat-tree network is only required to realize a set of N permutations needed for the N × N load-balanced Birkhoff-von Neumann switches. For this, we first derive a lower bound on the required degree for each node in a fat-tree network. By using the uniform mapping property of the bit-reverse permutation, we show that there exists a set of N permutations that achieve the lower bound.

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Beyond Fat--tree: Unidirectional Load--Balanced Multistage Interconnection Network

Cited by 15 publications

References 14 publications

Behavioral Model of Symmetrical Multi-Level T-Tree Interconnects

Behavioral Model of Symmetrical Multi-Level T-Tree Interconnects

Explicit Communication and Synchronization in SARC

Load-balanced Birkhoff-von Neumann switches and fat-tree networks

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