Beyond 16GB

Abstract

Stencil computations are a key class of applications, widely used in the scienti c computing community, and a class that has particularly bene ted from performance improvements on architectures with high memory bandwidth. Unfortunately, such architectures come with a limited amount of fast memory, which is limiting the size of the problems that can be e ciently solved. In this paper, we address this challenge by applying the well-known cache-blocking tiling technique to large scale stencil codes implemented using the OPS domain speci c language, such as CloverLeaf 2D, CloverLeaf 3D, and OpenSBLI. We introduce a number of techniques and optimisations to help manage data resident in fast memory, and minimise data movement. Evaluating our work on Intel's Knights Landing Platform as well as NVIDIA P100 GPUs, we demonstrate that it is possible to solve 3 times larger problems than the on-chip memory size with at most 15% loss in e ciency. ACM Reference format:

A Data-Centric Directive-Based Framework to Accelerate Out-of-Core Stencil Computation on a GPU

“…Reguly et al [21] presented a cache-blocking tiling technique that efficiently processes large scale stencil code. Their implementations are based on OPS [22]- [24]-a domain specific language (DSL) that requires implementing stencil code based on its syntax.…”

Preliminary Experience with OpenMP Memory Management Implementation

“…Some other initiatives also deal with high bandwidth memory management like MCDRAM for KNL processors. These forms of memory management have been explored within domain specific languages in [24].…”