Better by a HAIR: Hardware-amenable internet routing

Kiyak, Firat; Mochizuki, Brent; Keller, Eric; Caesar, Matthew

doi:10.1109/icnp.2009.5339694

Cited by 2 publications

(1 citation statement)

References 17 publications

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“…We are also applying our ideas to other lookup tasks in packet processing that can be implemented in SRAM-based pipelines [6]. Supporting in-architecture updates with little help from software [16] is also a promising topic to explore.…”

Section: B Fpga Prototypementioning

confidence: 99%

Towards Practical Architectures for SRAM-Based Pipelined Lookup Engines

Jiang

Prasanna

2010

2010 INFOCOM IEEE Conference on Computer Communications Workshops

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Abstract-Lookup engines for various network protocols can be implemented as tree-like search structures. Mapping such search structures onto static random addressable memory (SRAM) -based pipeline architectures has been studied as a promising alternative to ternary content addressable memory (TCAM) for high performance lookup engines in next generation routers. Incremental update and memory balancing are identified as two of the major challenges for the SRAM-based pipelined solutions to be practical. Although these two challenges have been separately addressed in some previous work, whether they can be solved simultaneously remains a question. Most of the existing mapping schemes to achieve balanced memory distribution across pipeline stages are static, where the entire search structure needs to be re-mapped to the pipeline once the lookup table has been updated. This paper takes IP lookup as a case study and proposes the incremental mapping scheme to support incremental updates while preserving balanced memory distribution across stages in a linear pipeline. We discuss two variants of the scheme and evaluate their performance in terms of memory balancing and update cost. Furthermore, we optimize the scheme to enable interfacing with external SRAMs so that even larger routing table can be supported using a single chip with limited onchip memory. Simulation using real-life routing tables validates our schemes. Prototype on a state-of-the-art field programmable gate array (FPGA) shows that our architecture can sustain 80 Gbps throughput for minimum size packets while supporting the currently largest routing table. We believe the proposed schemes can be applied to other SRAM-based pipelined lookup engines for various network protocols.

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Section: B Fpga Prototypementioning

confidence: 99%

Towards Practical Architectures for SRAM-Based Pipelined Lookup Engines

Jiang

Prasanna

2010

2010 INFOCOM IEEE Conference on Computer Communications Workshops

View full text Add to dashboard Cite

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Better by a HAIR: hardware-amenable Internet routing

Mochizuki¹,

Kiyak²,

Keller³

et al. 2011

Computer Networks

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Abstract-Routing protocols are implemented in the form of software running on a general-purpose microprocessor. However, conventional software-based router architectures face significant scaling challenges in the presence of ever-increasing routing table growth and churn. Recent advances in programmable hardware and high-level hardware description languages provide the opportunity to implement BGP directly at the hardware layer. Hardware-based implementation allows designs to take advantage of the parallelization and customizability of the underlying hardware to improve performance. As a first step in this direction, we design and implement a hardware-based BGP architecture. To understand the challenges in doing this, we propose an architecture and logical design for the core components of BGP running as a logical circuit in an FPGA. We then enumerate sources of complexity and performance bottlenecks, and derive modifications to BGP that reduce complexity of hardware offloading. Our results based on update traces from core Internet routers indicate an order of magnitude improvement in processing time and throughput.

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Better by a HAIR: Hardware-amenable internet routing

Cited by 2 publications

References 17 publications

Towards Practical Architectures for SRAM-Based Pipelined Lookup Engines

Towards Practical Architectures for SRAM-Based Pipelined Lookup Engines

Better by a HAIR: hardware-amenable Internet routing

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