Proceedings of the 42nd Annual Conference on Design Automation - DAC '05 2005
DOI: 10.1145/1065579.1065778
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BEOL variability and impact on RC extraction

Abstract: Historically, Back End of Line (BEOL) or interconnect resistance and capacitance have been viewed as parasitic components. They have now become key parameters with significant impact on circuit performance and signal integrity. This paper examines the types of BEOL variations and their impact on RC extraction. The importance of modeling systematic effects in RC extraction is discussed. The need for minimizing the computational error in RC extraction before incorporating random process variations is emphasized.

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Cited by 14 publications
(7 citation statements)
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“…The standard deviation of the wire length is calculated using (8) where α is a percentage of wire variation. α is found in accordance with the results from [18] as follows 1 :…”
Section: B2 Ssta Algorithmsupporting
confidence: 90%
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“…The standard deviation of the wire length is calculated using (8) where α is a percentage of wire variation. α is found in accordance with the results from [18] as follows 1 :…”
Section: B2 Ssta Algorithmsupporting
confidence: 90%
“…In the calculation of T R , we chose to use the sum of the mean and standard deviation since the result corresponds to the required clock frequency for an ~84% yield, for which we target in this study. After a 1 We plotted the equation based on the buffer size vs. wire variation data reported in [18]. …”
Section: B3 Floorplanner Cost Functionmentioning
confidence: 99%
“…Note that none of these distributions are Gaussian, since the extraction procedures which transform the physical parameters of interconnect lines to the corresponding electrical parameters are non-linear, and therefore, they tend to result in non-Gaussian distributions for the electrical parameters. This is in contrast with the Gaussian-based assumptions used typically in statistical timing analysis methodologies [12], [16]. The best maximum-likelihood fit for these distributions are lognormal distributions, parameters of which are listed in Table 1 with confidence level of 98%.…”
Section: Statistical Modelmentioning
confidence: 99%
“…This is in turn due to effects of the neighboring interconnect lines, non-uniform metal densities, NonLinear Resistance (NLR) effect, Selective Process Bias (SPB) [12] effect, and thickness variation due to etching and CMP (Chemical Mechanical Polishing). Other sources of variation are die-to-die, wafer-to-wafer, lot-to-lot, and fab-to-fab variations.…”
Section: Interconnect Sources Of Variationmentioning
confidence: 99%
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