BEOL process integration with Cu/SiCOH (k=2.8) low-k interconnects at 65 nm groundrules

Fukasawa, Masanaga; Lane, S.; Angyal, M.; Chanda, Kaushik; Chen, F.; Christiansen, C.; Fitzsimmons, J.; Gill, Jason M.R.; Ida, K.; Inoue, Ken; Kumar, Kaushik; Li, B.; McLaughlin, P.; Melville, Ian; Minami, Masashi; Nguyen, S.; Penny, C.; Sakamoto, Atsushi; Shimooka, Y.; Ono, Masayuki; McHerron, D.; Nogami, Takeshi; Ivers, T.

doi:10.1109/iitc.2005.1499904

Cited by 6 publications

(4 citation statements)

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“…The dielectrics of SiN, SiNO, SiCN, SiCOH, pSiCOH for pinch off deposition were deposited in a commercial high throughput production-worthy 13.6 MHz RF 300 mm Plasma Chemical Vapor Deposition process (PECVD) system at 350 C. The dielectrics were deposited using a combination of various silane (SiH4) or carbosilane or organosilicon precursors with other reactant gases such as Ammonia ((NH 3 ), Nitrogen (N 2 ), Oxygen (O 2 ), or Nitrous Oxide (N 2 O) as described in previous publications. [12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29] The advanced highly robust conformal SiN 6 was deposited by cyclic processing using Silane, Ammonia and Nitrogen. The SiCN dielectric was also deposited at 350 C using a combination of Trimethyl Silane (TMS) + Ammonia (NH 3 ) and (optionally) with Hydrogen for robust SiCN film.…”

Section: Experiment-film Deposition and Pinch Off Processmentioning

confidence: 99%

“…21,22 Table I summarizes various plasma deposited dielectric films and their properties. These dielectric films have been developed and used by our laboratories and have appeared in many of our publications [12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29] over the years. Since similar materials can be deposited under various conditions and have different properties, our reference publications [12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29] is to prefer to specific process chemistry and tooling that use for this pinch off deposition processes.…”

Section: Experiment-film Deposition and Pinch Off Processmentioning

confidence: 99%

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Pinch Off Plasma CVD Deposition Process and Material Technology for Nano-Device Air Gap/Spacer Formation

Nguyen¹,

Haigh²,

Cheng³

et al. 2018

ECS J. Solid State Sci. Technol.

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As integrated circuits for high performance CMOS devices scale down to < = 10 nm dimension, further reductions in capacitance are vitally important for device performance. It is important to reduce capacitance in the FEOL and BEOL device structures while maintaining fabrication integration robustness. This paper presents an overview of material and process technology requirements for FEOL air spacer and BEOL air gap formation using a pinch off deposition approach. These approaches utilize established dielectric materials and processes such as Plasma CVD of SiN, SiCN, SiCOH, pSiCOH, in the formation of the air spacer/air gap. The selection of these dielectric materials and processes has a large impact in the void (gap) dimension and volume. The void dimension and volume in airgap/air spacer structures can be controlled with various dielectric deposition processes and materials to facilitate subsequent process fabrication steps, and ultimately to build a robust device with substantial capacitance reduction.

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Section: Experiment-film Deposition and Pinch Off Processmentioning

confidence: 99%

Section: Experiment-film Deposition and Pinch Off Processmentioning

confidence: 99%

Pinch Off Plasma CVD Deposition Process and Material Technology for Nano-Device Air Gap/Spacer Formation

Nguyen¹,

Haigh²,

Cheng³

et al. 2018

ECS J. Solid State Sci. Technol.

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“…The via-first dual damascene scheme was used [16]. The process flow, each process step, the dimension of each metal layer/via and the tool set are basically the same as those used in our standard 65 nm BEOL integrations which use k=3.0 SiCOH films at 1X, 2X and 4X wires.…”

Section: -1 Interconnect Schemementioning

confidence: 99%

Low-k/copper integration scheme suitable for ULSI manufacturing from 90nm to 45nm nodes

Nogami

Lane²,

Fukasawa

et al. 2005

SPIE Proceedings

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This paper discusses low-k/copper integration schemes which has been in production in the 90 nm node, have been developed in the 65 nm node, and should be taken in the 45 nm node. While our baseline 65 nm BEOL process has been developed by extension and simple shrinkage of our PECVD SiCOH integration which has been in production in the 90 nm node with our SiCOH film having k=3.0, the 65 nm SiCOH integration has two other options to go to extend to lower capacitance. One is to add porosity to become ultra low-k (ULK). The other is to stay with low-k SiCOH, which is modified to have a "lower-k". The effective k-value attained with the lower-k (k=2.8) SiCOH processed in the "Direct CMP" scheme is very close to that with an ULK (k=2.5) SiCOH film built with the "Hard Mask Retention" scheme. This paper first describes consideration of these two damascene schemes, whose comparison leads to the conclusion that the lower-k SiCOH integration can have more advantages in terms of process simplicity and extendibility of our 90 nm scheme under certain assumptions. Then describing the k=2.8 SiCOH film development and its successful integration, damascene schemes for 45nm nodes are discussed based on our learning from development of the lower-k 65nm scheme. Capability of modern dry etchers to define the finer patterns, nonuniformity of CMP, and susceptibility to plasma and mechanical strength and adhesion of ULK are discussed as factors to hamper the applicability of ULK.

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“…However, integration of porous low-k materials into Cu interconnects is a significant challenge due to poor mechanical strength as increasing the film porosity to reduce initial k-value for interlayer dielectric (ILD) film, the processinduced damage on ILD, and reliability issues. [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18] To use a dielectric material, which itself is resistant to physical and chemical damage, is very important. As the continued technology scaling, the development of the low-k materials is very difficult due to the achievable k-value is shifted to later technology generation by description of International Technology Roadmap for Semiconductors (ITRS).…”

mentioning

confidence: 99%

Film deposition and UV curing process impact on ultralow-kdielectric for high performance Cu interconnects

Gu¹,

Deng²,

Tong³

et al. 2017

Jpn. J. Appl. Phys.

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Ultralow-k (ULK) film deposition and UV curing process were studied to explore the effects on the mechanical, electrical and chemical properties of ULK dielectrics. UV curing process plays an important role to enhance the Young’s modulus (mechanical performance) by increasing the formation of –Si–O–Si– cross-linking, and ULK film deposition with low film shrinkage ratio can form a robust porous SiOCH to avoid following integration process-induced damage on ULK dielectrics and also improve the device reliability performance significantly.

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BEOL process integration with Cu/SiCOH (k=2.8) low-k interconnects at 65 nm groundrules

Cited by 6 publications

References 0 publications

Pinch Off Plasma CVD Deposition Process and Material Technology for Nano-Device Air Gap/Spacer Formation

Pinch Off Plasma CVD Deposition Process and Material Technology for Nano-Device Air Gap/Spacer Formation

Low-k/copper integration scheme suitable for ULSI manufacturing from 90nm to 45nm nodes

Film deposition and UV curing process impact on ultralow-kdielectric for high performance Cu interconnects

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