BEOL process integration for the 7 nm technology node

Standaert, T.; Beique, Genevieve; Chen, H.-C.; Chen, S.-T.; Hamieh, Bassem; Lee, J.; McLaughlin, P.; McMahon, Jeffrey M.; Mignot, Yann; Mont, Frank W.; Motoyama, K.; Nguyen, S.; Patlolla, R.; Peethala, B.; Priyadarshini, Deepika; Rizzolo, Michael; Saulnier, Nicole; Shobha, H.; Siddiqui, S.; Spooner, T.; Tang, Hao; Straten, O. van der; Verduijn, Erik; Xu, Yuheng; Zhang, X.; Arnold, John; Canaperi, D.; Colburn, Matthew; Edelstein, D.; Paruchuri, Vamsi; Bonilla, G.

doi:10.1109/iitc-amc.2016.7507636

Cited by 31 publications

(15 citation statements)

References 5 publications

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“…The mean values for the parameters are obtained from recent experimental reports on modern manufacturing processes [4][5][6][7]. This model confirms that for novel technologies [12][13][14][15][16][17], neglecting the temperature evolution and its impact on interconnect reliability and their lifetime may lead to wrong conclusions or catastrophic failures.…”

Section: Materials Migrationsupporting

confidence: 67%

“…However, the corresponding current and the interconnect width are used appropriately. The mean values for the parameters are obtained from recent experimental reports on modern manufacturing processes of major foundries [4][5][6][7] [13][14][15][16][17]. Due to the space limit, the effects are shown for local interconnects only; similar observations can be made for other layers.…”

Section: Temperature In Interconnectsmentioning

confidence: 98%

“…The segment is then properly constructed in COMSOL Multiphysics [12]. The values for geometrical, electrical, mechanical and thermal properties of technology are obtained from various recent reports of major foundries for 10nm [4][5][6] [13][14][15][16][17]. Via effect which explains the inter-layer heat transfer is also employed for realistic and accurate modeling [1] [9].…”

Section: Temperature In Interconnectsmentioning

confidence: 99%

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Non-Uniform Temperature Distribution in Interconnects and Its Impact on Electromigration

Abbasinasab

Marek-Sadowska

2019

Proceedings of the 2019 Great Lakes Symposium on VLSI

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We investigate the effect of electrically induced thermal load on interconnect reliability and aging. We propose new models for uniform and non-uniform temperature evolution and its steady state distribution in interconnects considering Joule heating and heat convection. The models are verified by comparing the results against those of finite element experiments. We apply our models to study material migration induced aging and failures. We discuss how different non-uniform temperature profiles affect interconnect lifetime. We propose new formulas for accurate temperature aware assessment of the mortality of interconnects. We demonstrate that neglecting thermal effects in modern technologies may lead to incorrect conclusions about interconnect mortality. We also provide a method for modeling the true mean time to failure based on underlying physics.

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Section: Materials Migrationsupporting

confidence: 67%

Section: Temperature In Interconnectsmentioning

confidence: 98%

Section: Temperature In Interconnectsmentioning

confidence: 99%

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Non-Uniform Temperature Distribution in Interconnects and Its Impact on Electromigration

Abbasinasab

Marek-Sadowska

2019

Proceedings of the 2019 Great Lakes Symposium on VLSI

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“…Pattern wafers were fabricated using standard trench first metal hardmask damascene scheme to create a line pattern of 36 nm pitch with single EUV exposures using low k OMCTS 2.7 as the dielectric. 16 A line pattern was exposed and directly transferred into a metal hardmask film. The main etch then transferred the line pattern from the metal hardmask onto the dielectric film (ULK k2.7).…”

Section: ■ Experimental Sectionmentioning

confidence: 99%

Fifteen Nanometer Resolved Patterns in Selective Area Atomic Layer Deposition—Defectivity Reduction by Monolayer Design

Wojtecki

Mettry

Nathel

et al. 2018

ACS Appl. Mater. Interfaces

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Selective area atomic layer deposition (SA-ALD) offers the potential to replace a lithography step and provide a significant advantage to mitigate pattern errors and relax design rules in semiconductor fabrication. One class of materials that shows promise to enable this selective deposition process are self-assembled monolayers (SAMs). In an effort to more completely understand the ability of these materials to function as barriers for ALD processes and their failure mechanism, a series of SAM derivatives were synthesized and their structureproperty relationship explored. These materials incorporate different side group functionalities and were evaluated in the deposition of a sacrificial etch mask. Monolayers with weak supramolecular interactions between components (for example, van der Waals) were found to direct a selective deposition, though they exhibit significant defectivity at and below 100 nm feature sizes. The incorporation of stronger noncovalent supramolecular interacting groups in the monolayer design, such as hydrogen bonding units or pi–pi interactions, did not produce an added benefit over the weaker interacting components. Incorporation of reactive moieties in the monolayer component that enabled the polymerization of an SAM surface, however, provided a more effective barrier, greatly reducing the number and types of defects observed in the selectively deposited ALD film. These reactive monolayers enabled the selective deposition of a film with critical dimensions as low as 15 nm. It was also found that the selectively deposited film functioned as an effective barrier for isotropic etch chemistries, allowing the selective removal of a metal without affecting the surrounding surface. This work enables selective area ALD as a technology through (1) the development of a material that dramatically reduces defectivity and (2) the demonstrated use of the selectively deposited film as an etch mask and its subsequent removal under mild conditions.

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“…The overall cost of the resulting CGRA architecture is evaluated by measuring the area of the resulting architecture and the energy consumption. Similar to other state of the art related works [29,30], we estimate the area occupancy of our architecture while assuming a 7 nm lithography technology. Thus, a 6T SRAM bit cell unit's size is 30 nm 2 , i.e., 38.5 Mb in 1 mm 2 .…”

Section: Area and Energy Estimationsmentioning

confidence: 99%

Creating Customized CGRAs for Scientific Applications

2021

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Executing complex scientific applications on Coarse Grain Reconfigurable Arrays (CGRAs) offers improvements in the execution time and/or energy consumption when compared to optimized software implementations or even fully customized hardware solutions. In this work, we explore the potential of application analysis methods in such customized hardware solutions. We offer analysis metrics from various scientific applications and tailor the results that are to be used by MC-Def, a novel Mixed-CGRA Definition Framework targeting a Mixed-CGRA architecture that leverages the advantages of CGRAs and those of FPGAs by utilizing a customized cell-array along, with a separate LUT array being used for adaptability. Additionally, we present the implementation results regarding the VHDL-created hardware implementations of our CGRA cell concerning various scientific applications.

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BEOL process integration for the 7 nm technology node

Cited by 31 publications

References 5 publications

Non-Uniform Temperature Distribution in Interconnects and Its Impact on Electromigration

Non-Uniform Temperature Distribution in Interconnects and Its Impact on Electromigration

Fifteen Nanometer Resolved Patterns in Selective Area Atomic Layer Deposition—Defectivity Reduction by Monolayer Design

Creating Customized CGRAs for Scientific Applications

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