2020 IEEE 70th Electronic Components and Technology Conference (ECTC) 2020
DOI: 10.1109/ectc32862.2020.00231
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BEOL-Embedded 3D Polylithic Integration: Thermal and Interconnection Considerations

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Cited by 12 publications
(1 citation statement)
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“…To be specific, we considered the transistor parameter degradation ratio between the top tier and the bottom substrate of the silicon transistors, as shown in the experimental data for the top tier laser-recrystallized silicon transistors [43]. Furthermore, we also considered the heat dissipation in M3D architecture, by introducing a compact model of the thermal profile [44] into the M3D benchmark framework accounting for (a) top and bottom tiers' power density; (b) the chip area and substrate thickness; and (c) inter-tier BEOL thickness and material. Fig.…”
Section: Monolithic 3d Integrationmentioning
confidence: 99%
“…To be specific, we considered the transistor parameter degradation ratio between the top tier and the bottom substrate of the silicon transistors, as shown in the experimental data for the top tier laser-recrystallized silicon transistors [43]. Furthermore, we also considered the heat dissipation in M3D architecture, by introducing a compact model of the thermal profile [44] into the M3D benchmark framework accounting for (a) top and bottom tiers' power density; (b) the chip area and substrate thickness; and (c) inter-tier BEOL thickness and material. Fig.…”
Section: Monolithic 3d Integrationmentioning
confidence: 99%