BenchNN: On the broad potential application scope of hardware neural network accelerators

Chen, Tianshi; Duranton, Marc; Guo, Qi; Hashmi, Atif; Lipasti, Mikko H.; Nere, Andrew; Qiu, Shi; Sebag, Michèle; Temam, Olivier

doi:10.1109/iiswc.2012.6402898

Cited by 90 publications

(41 citation statements)

References 29 publications

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“…The main goal of our research [1,2,4,3] is to show that hardware neural network accelerators are not just a nice concept, but a proposition with real value in the current technology and application context.…”

Section: A Nice Concept or For Real ?mentioning

confidence: 99%

Hardware neural network accelerators

Temam¹

2013

2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)

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TOWARDS ACCELERATORSBecause of increasingly stringent energy constraints (e.g., Dark Silicon, there is a growing consensus in the community that we may be moving towards heterogeneous multi-core architectures, composed of a mix of cores and accelerators. Because our community is traditionally focused on general-purpose computing, we have been especially considering accelerator approaches such as GPUs and reconfigurable circuits. An attractive alternative is to investigate accelerators which are focused on a few key algorithms: key algorithms still mean broad application scope, but few algorithms enable energy efficient and cost-effective accelerators.Assuming we want to go down the path of multi-purpose accelerators for energy reasons, the main question becomes: which applications should be considered ? The PARSEC benchmarks have been introduced to highlight a trend towards a new kind of high-performance applications (e.g., voice recognition, image analysis, navigation, etc). Interestingly, many of the core tasks of these benchmarks turn out to correspond to inherently stochastic algorithms/tasks, such as clustering, classification, optimization, filtering, approximation algorithms, i.e., tasks which are inherently tolerant to a certain degree of inaccuracy.What accelerator design would then be appropriate ? When considering the need for energy efficiency and faults/defects tolerance, as well as the nature of the emerging high-performance applications, hardware neural networks come across as an attractive alternative accelerator design. While Neural Networks (NNs) are often considered as a niche application, one can consider all the aforementioned applications: many of the emerging high-performance applications are based on machine-learning techniques, and there are competitive alternatives based on neural networks for all five aforementioned core algorithms (clustering, classification, optimization, filtering, approximation). As a result, NNs are much more a kernel based on which many applications can be developed rather than a niche algorithm. At the same time, an NN circuit is much closer to an ASIC than a processor, so an NN accelerator can potentially achieve the energy efficiency of an ASIC while still having the broad aforementioned application scope. Finally, one of the most attractive properties of neural networks are their inherent robustness to faults. Thanks to its learning algorithm, an NN can automatically silence out faulty parts through retraining, without having to identify or disable these faults, an attractive feature. WHY HARDWARE NEURAL NETWORKS AGAIN ?Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee.However, NNs are certainly not a new c...

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Section: A Nice Concept or For Real ?mentioning

confidence: 99%

Hardware neural network accelerators

Temam¹

2013

2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)

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“…The motivation behind this research work is twofold: 1) An application specific design allows small footprint per accelerator, which allow including a rich set of accelerators in the system. 2) Many modern applications can be solved by using neural networks [40].…”

Section: B Custom and Reconfigurable Logic Acceleratorsmentioning

confidence: 99%

Hardware accelerator design for data centers

Yesil¹,

Özdal²,

Ayupov³

et al. 2015

2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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As the size of available data is increasing, it is becoming inefficient to scale the computational power of traditional systems. To overcome this problem, customized applicationspecific accelerators are becoming integral parts of modern system on chip (SOC) architectures. In this paper, we summarize existing hardware accelerators for data centers and discuss the techniques to implement and embed them along with the existing SOCs.

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“…In an effort to broaden the applicability of NNs, Chen et al [10] have developed software NN implementations of high performance applications from the PARSEC [5] suite.…”

Section: Neural Network Implementationsmentioning

confidence: 99%

BRAINIAC: Bringing reliable accuracy into neurally-implemented approximate computing

Grigorian¹,

Farahpour²,

Reinman³

2015

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)

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Applications with large amounts of data, real-time constraints, ultra-low power requirements, and heavy computational complexity present significant challenges for modern computing systems, and often fall within the category of high performance computing (HPC). As such, computer architects have looked to high performance single instruction multiple data (SIMD) architectures, such as accelerator-rich platforms, for handling these workloads. However, since the results of these applications do not always require exact precision, approximate computing may also be leveraged. In this work, we introduce BRAINIAC, a heterogeneous platform that combines precise accelerators with neural-network-based approximate accelerators. These reconfigurable accelerators are leveraged in a multi-stage flow that begins with simple approximations and resorts to more complex ones as needed. We employ high-level, applicationspecific light-weight checks (LWCs) to throttle this multi-stage acceleration flow and reliably ensure user-specified accuracy at runtime. Evaluation of the performance and energy of our heterogeneous platform for error tolerance thresholds of 5%-25% demonstrates an average of 3× gain over computation that only includes precise acceleration, and 15×-35× gain over softwarebased computation.

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BenchNN: On the broad potential application scope of hardware neural network accelerators

Cited by 90 publications

References 29 publications

Hardware neural network accelerators

Hardware neural network accelerators

Hardware accelerator design for data centers

BRAINIAC: Bringing reliable accuracy into neurally-implemented approximate computing

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