Benchmarking for large-scale placement and beyond

Abstract

Over the last five years the VLSI Placement community achieved great strides in the understanding of placement problems, developed new high-performance algorithms, and achieved impressive empirical results. These advances have been supported by nontrivial benchmarking infrastructure, and future achievements are set to draw on benchmarking as well. In this paper we review motivations for benchmarking, especially for commercial EDA, analyze available benchmarks, and point out major pitfalls in benchmarking. We outline major outstanding problems and discuss the future of placement benchmarking. Furthermore, we attempt to extrapolate our experience to circuit layout tasks beyond placement.

Force directed module placement with pin consideration

“…Therefore as the final step, the Capo legalizer [3] is applied in order to remove any overlaps present and to ensure that the cells are within the placement area.…”

“…However, it has been identified in several research work [3,4] that established classical standard cell placement techniques are not adequate for current complex designs due to changes of requirements (e.g. increased number of cells, high utilization targets, mixed cell usage etc.).…”

Early research experience with OpenAccess gear

“…Third, open source encourages others to build on existing work and return improvements back to the community, benefiting all. The advantages of open source are well-known in the physical design community; see for instance [7,18].…”

“…Timing is a much-neglected area in academic physical design research, with a lack of generally accepted infrastructure [7]. The essential difficulties are:…”

“…Finally, the lack of common infrastructure makes comparison of results between different tools problematic. Both [7] and [18] discuss this particular issue in detail.…”