Benchmarking for large-scale placement and beyond

Adya, Saurabh; Yıldız, Mehmet; Markov, Igor L.; Villarrubia, Paul G.; Parakh, Phiroze N.; Madden, Patrick H.

doi:10.1145/640000.640022

Cited by 36 publications

(43 citation statements)

References 40 publications

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“…Finally, the lack of common infrastructure makes comparison of results between different tools problematic. Both [97] and [98] discuss this particular issue in detail.…”

Section: Openaccessmentioning

confidence: 99%

Integrated logic synthesis using simulated annealing

Färm

Dubrova

Kuehlmann

2011

Proceedings of the 21st Edition of the Great Lakes Symposium on Great Lakes Symposium on VLSI

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KTH School of Information andCommunication Technology SE-164 40 Kista SWEDEN Akademisk avhandling som med tillstånd av Kungl Tekniska högskolan framlägges till offentlig granskning för avläggande av teknologie doktorsexamen i elektronik fredagen den 26 januari 2007 klockan 9.00 i Sal E, Forumhuset, Kungl Tekniska högskolan, Isafjordsgatan 39, Kista. © Petra Färm, januari 2007Tryck: Universitetsservice US AB iii Abstract A conventional logic synthesis flow is composed of three separate phases: technology independent optimization, technology mapping, and technology dependent optimization. A fundamental problem with such a three-phased approach is that the global logic structure is decided during the first phase without any knowledge of the actual technology parameters considered during later phases. Although technology dependent optimization algorithms perform some limited logic restructuring, they cannot recover from fundamental mistakes made during the first phase, which often results in non-satisfiable solutions.We present a global optimization approach combining technology independent optimization steps with technology dependent objectives in an annealing-based framework. We prove that, for the presented move set and selection distribution, detailed balance is satisfied and thus the annealing process asymptotically converges to an optimal solution. Furthermore, we show that the presented approach can smoothly trade-off complex, multiple-dimensional objective functions and achieve competitive results. The combination of technology independent and technology dependent objectives is handled through dynamic weighting. Dynamic weighting reflects the sensitivity of the local graph structures with respect to the actual technology parameters such as gate sizes, delays, and power levels. The results show that, on average, the presented advanced annealing approach can improve the area and delay of circuits optimized using the Boolean optimization technique provided by SIS with 11.2% and 32.5% respectively.Furthermore, we demonstrate how the developed logic synthesis framework can be applied to two emerging technologies, chemically assembled nanotechnology and molecule cascades. New technologies are emerging because a number of physical and economic factors threaten the continued scaling of CMOS devices. Alternatives to silicon VLSI have been proposed, including techniques based on molecular electronics, quantum mechanics, and biological processes. We are hoping that our research in how to apply our developed logic synthesis framework to two of the emerging technologies might provide useful information for other designers moving in this direction.iv

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“…Finally, the lack of common infrastructure makes comparison of results between different tools problematic. Both [97] and [98] discuss this particular issue in detail.…”

Section: Openaccessmentioning

confidence: 99%

Integrated logic synthesis using simulated annealing

Färm

Dubrova

Kuehlmann

2011

Proceedings of the 21st Edition of the Great Lakes Symposium on Great Lakes Symposium on VLSI

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“…Capo uniformly spreads [3] the available whitespace throughout the core region. We briefly explain the whitespace allocation strategy implemented in Capo [8].…”

Section: Hierarchical Whitespace Allocation In Top-down Placementmentioning

confidence: 99%

“…Routability of Capo and Dragon placements on ibm-Dragon benchmarks is discussed in [3], where, the differences are traced to greater horizontal wirelength and smaller vertical wirelength in Capo placements.…”

Section: Free Cellsmentioning

confidence: 99%

“…With the rapid decrease of feature sizes, circuit layouts become more complex, both in terms of size and design constraints [3]. To achieve timing closure for high-performance circuits, it is now common to use physical synthesis -an approach that combines logic and physical optimization, potentially performing placement-aware buffer insertion, gate sizing, fanout optimization, etc.…”

Section: Introductionmentioning

confidence: 99%

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On whitespace and stability in physical synthesis

Adya¹,

Markov

Villarrubia

2006

Integration

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“…A convergence on metrics and benchmarks [18], [1] has allowed direct comparison of results. The PEKO benchmarks [5] showed how far current tools were from optimal, and how much performance gain was possible through better placement.…”

Section: Discussionmentioning

confidence: 99%

On structure and suboptimality in placement

Ono¹,

Madden²

Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.

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Abstract-Regular structures are present in many types of circuits. If this structure can be identified and utilized, performance can be improved dramatically. In this paper, we present a novel placement approach that successfully identifies regularity, and obtains placements that are superior to other "general purpose" methods. This method has been integrated into our Feng Shui 2.6 bisection-based placement tool.On experiments with the PEKO benchmarks, our results are within 32% of optimal for both the large and small suites. The largest example, with 2.1 million cells, can be completed in sixteen hours. The majority of our run time is during detail placementglobal placement takes under three hours. The success of our method shows that it can find structure, even when the structure was not expected or intended.As part of this work, we have made a number of observations related to the nature of suboptimality in placement. These observations have shown that some neglected research areas have great potential, while problems that receive considerable attention are essentially adequately solved.

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Benchmarking for large-scale placement and beyond

Cited by 36 publications

References 40 publications

Integrated logic synthesis using simulated annealing

Integrated logic synthesis using simulated annealing

On whitespace and stability in physical synthesis

On structure and suboptimality in placement

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