Benchmarking for Large-Scale Placement and Beyond

Abstract

Over the last five years the VLSI Placement community achieved great strides in the understanding of placement problems, developed new high-performance algorithms, and achieved impressive empirical results. These advances have been supported by nontrivial benchmarking infrastructure, and future achievements are set to draw on benchmarking as well. In this paper we review motivations for benchmarking, especially for commercial EDA, analyze available benchmarks, and point out major pitfalls in benchmarking. We outline major outstanding problems and discuss the future of placement benchmarking. Furthermore, we attempt to extrapolate our experience to circuit layout tasks beyond placement.

Effective Wire Models for X-Architecture Placement

“…We used the benchmark "IBM version 2.0," which is widely used in academia [15]. Although not reported here, the results on the ISPD'05 and ISPD'06 Placement Contest Benchmarks [16], [17] are similar.…”

Memetic multilevel hypergraph partitioning

“…To this end, we present sophisticated recombination and mutation operators as well as a replacement rule that uses a problem specific similarity measure. In contrast to previous work [6,7,8,15,38], which only considered small and outdated [1,3] ACM/SIGDA benchmark instances [46] (dating back to the late 1980s), we perform extensive experiments on a large benchmark set containing hypergraphs from several application areas. Our experiments indicate that our algorithm is able to compute partitions of very high quality and scales well to large networks.…”