Behavioral Modeling of Steady-State Oscillators with Buffers Using Neural Networks

Yu, Huan; Chalamalasetty, Hemanth; Swaminathan, Madhavan

doi:10.1109/epeps.2018.8534238

Cited by 11 publications

(3 citation statements)

References 7 publications

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“…It suffers from triggering the state transitions for the waveforms with flat regions such as in trapezoidal oscillatory waveforms. In [8] and [9], alternate approaches have been proposed. These models, however, do not take into account the voltage-controlled variation of the frequency.…”

Section: Introductionmentioning

confidence: 99%

“…The implementation in Verilog-A makes the proposed model compatible with many commercial tools [10]. This paper significantly expands the content in [9] and [11], by proposing the formulation of AugNNs using multiple output neurons with a corresponding gradient scheme to address the modeling of multi-phase oscillators. The proposed method also addresses the voltage-controlled variation characteristics of oscillators and the associated port behavior when the buffer is included as part of the oscillator design.…”

Section: Introductionmentioning

confidence: 99%

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Modeling of Voltage-Controlled Oscillators Including I/O Behavior Using Augmented Neural Networks

Chalamalasetty

Swaminathan

2019

IEEE Access

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This paper proposes augmented neural networks (AugNNs) for modeling the behavior of steady-state oscillators in time-domain. Multi-output AugNNs with the corresponding gradient scheme and training methodology are proposed for the modeling of multi-phase oscillators. Using the proposed AugNNs, a novel technique is presented for the modeling of voltage-controlled oscillators (VCOs) including I/O behavior. In the proposed AugNNs, a periodic unit is introduced to capture the relation between the instantaneous frequency and the control signal, and to provide the phase information of the oscillation, which is used to predict the oscillatory output waveforms using feed forward neural networks (FFNN). For the modeling of VCOs including output buffers, an AugNN-based model is proposed, where recurrent neural networks (RNNs) are used to capture the nonlinear dynamic current-voltage relation at the output port. The simulated data of transistor-level oscillator circuit are used to train the proposed model. As a black-box approach, the proposed model protects intellectual property (IP) and can be implemented in Verilog-A. The examples using transistor-level oscillator circuits demonstrate the effectiveness of the proposed model for time-domain analysis.INDEX TERMS Behavioral modeling, voltage-controlled oscillator (VCO), neural network, output buffer, Verilog-A.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Modeling of Voltage-Controlled Oscillators Including I/O Behavior Using Augmented Neural Networks

Chalamalasetty

Swaminathan

2019

IEEE Access

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“…Using neural networks (NN) has been previously suggested to generate surrogate models for nonlinear circuits. In [21] and [22], recurrent NNs is used to model nonlinear I/O drivers, and in [23] recurrent NNs is used to model SerDes channels. However, training neural networks is generally more complicated and time consuming compared to PC models.…”

Section: Introductionmentioning

confidence: 99%

A Hybrid Methodology for Jitter and Eye Estimation in High-Speed Serial Channels Using Polynomial Chaos Surrogate Models

et al. 2019

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Estimation of jitter and eye diagram in high-speed serial channels can be challenging. The existing methods might fail to show inter-symbol interference (ISI) and data dependent jitter because they are either excessively time consuming or only applicable to linear time-invariant (LTI) systems. Therefore, this paper suggests a hybrid methodology to develop surrogate models of the system from a short transient simulation and using them to efficiently determine the eye diagram and related parameters. This paper is based on uncertainty quantification techniques that use polynomial chaos (PC) expansions to estimate the output. Necessary modifications are applied to PC modeling to make it applicable to high-speed channels. Finally, the performance of the proposed approach is shown through numerical examples. INDEX TERMS Signal integrity, eye diagram, jitter, high-speed channel, machine learning, polynomial chaos, statistical analysis.

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Determining worst-case eye height in low BER channels using Bayesian optimization

Dolatsara

Swaminathan

2020

2020 IEEE 11th Latin American Symposium on Circuits &Amp; Systems (LASCAS)

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Behavioral Modeling of Steady-State Oscillators with Buffers Using Neural Networks

Cited by 11 publications

References 7 publications

Modeling of Voltage-Controlled Oscillators Including I/O Behavior Using Augmented Neural Networks

Modeling of Voltage-Controlled Oscillators Including I/O Behavior Using Augmented Neural Networks

A Hybrid Methodology for Jitter and Eye Estimation in High-Speed Serial Channels Using Polynomial Chaos Surrogate Models

Determining worst-case eye height in low BER channels using Bayesian optimization

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