Real-time systems, characterized by a set of timings constants (internal delays, timers, clock speeds), need to be perfectly reliable. Formal methods can prove their correctness but, if one of the timing constants changes, verification needs to be restarted from scratch. Also, variations of some delays (even infinitesimal) may lead to the specification violation. It is thus interesting to reason parametrically, and synthesize constraints on the timing constants seen as parameters to formally guarantee the specification. We propose here an attempt to distribute a synthesis algorithm, the behavioral cartography, and we evaluate two work distribution algorithms. The parallelization gives promising results and opens perspectives toward verification of larger models.