Beating in-order stalls with "flea-flicker" two-pass pipelining

Barnes, R. D.; Patel, Sanjay J.; Nyström, Erik; Navarro, Nacho; Sias, John W.; Hwu, Wen-mei W.

doi:10.1109/micro.2003.1253243

Cited by 29 publications

(18 citation statements)

References 17 publications

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“…Besides the flexibility of supporting multithreaded workloads, it eliminates the need for any centralized resources compared to out-of-order processors with large instruction windows [1], [11], [16], [33], two-pass/multipass in-order pipelining [4], [5], or decoupled kilo-instruction processors [24]. Run-ahead execution [12], [23] is another alternative to large instruction windows which does not require any large centralized structures.…”

Section: Related Workmentioning

confidence: 99%

Submitted to IEEE Transactions on Parallel and Distributed Systems Special Issue on CMP Architectures

Gao

Dimitrov

et al. 2015

IEEE Trans. Parallel Distrib. Syst.

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Dual-core execution (DCE) is an execution paradigm proposed to utilize chip multiprocessors to improve the performance of single-threaded applications. Previous research has shown that DCE provides a complexity-effective approach to building a highly scalable instruction window and achieves significant latency-hiding capabilities. In this paper, we propose to optimize DCE for power efficiency and/or transient-fault recovery. In DCE, a program is first processed (speculatively) in the front processor and then reexecuted by the back processor. Such reexecution is the key to eliminating the centralized structures that are normally associated with very large instruction windows. In this paper, we exploit the computational redundancy in DCE to improve its reliability and its power efficiency. The main contributions include: 1) DCE-based redundancy checking for transient-fault tolerance and a complexity-effective approach to achieving full redundancy coverage and 2) novel techniques to improve the power/energy efficiency of DCE-based execution paradigms. Our experimental results demonstrate that, with the proposed simple techniques, the optimized DCE can effectively achieve transientfault tolerance or significant performance enhancement in a power/energy-efficient way. Compared to the original DCE, the optimized DCE has similar speedups (34 percent on average) over single-core processors while reducing the energy overhead from 93 percent to 31 percent.

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Section: Related Workmentioning

confidence: 99%

Submitted to IEEE Transactions on Parallel and Distributed Systems Special Issue on CMP Architectures

Gao

Dimitrov

et al. 2015

IEEE Trans. Parallel Distrib. Syst.

View full text Add to dashboard Cite

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“…The common explanation for the IO/OOO performance disparity is that the OOO is inherently better at exploiting memory-level parallelism as even the most sophisticated static schedule is hobbled by the stall-on-use/head-of-line blocking problem inherent to cache misses in IO designs [2,22]. In contrast, the enduring trend over several generations of OOO designs is their ability to toler-…”

Section: The Perceived Out-of-order Performance Advantagementioning

confidence: 99%

Discerning the dominant out-of-order performance advantage

McFarlin¹,

Tucker

Zilles

2013

Proceedings of the Eighteenth International Conference on Architectural Support for Programming Languages and Operating Systems

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In this paper, we set out to study the performance advantages of an Out-of-Order (OOO) processor relative to in-order processors with similar execution resources. In particular, we try to tease apart the performance contributions from two sources: the improved schedules enabled by OOO hardware speculation support and its ability to generate different schedules on different occurrences of the same instructions based on operand and functional unit availability. We find that the ability to express good static schedules achieves the bulk of the speedup resulting from OOO. Specifically, of the 53% speedup achieved by OOO relative to a similarly provisioned inorder machine, we find that 88% of that speedup can be achieved by using a single "best" static schedule as suggested by observing an OOO schedule of the code. We discuss the ISA mechanisms that would be required to express these static schedules.Furthermore, we find that the benefits of dynamism largely come from two kinds of events that influence the application's critical path: load instructions that miss in the cache only part of the time and branch mispredictions. We find that much of the benefit of OOO dynamism can be achieved by the potentially simpler task of addressing these two behaviors directly.

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“…Examples include Continual Flow Pipelines [26], Runahead Execution [19] and Flea-Flicker Pipelining [6]. Such techniques enhance and extend existing structures for speculative execution of a single thread to allow a large number of instructions from the same thread to be in flight at the same time.…”

Section: Related Workmentioning

confidence: 99%

Increasing memory miss tolerance for SIMD cores

Tarjan

Meng

Skadron

2009

Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis

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Manycore processors with wide SIMD cores are becoming a popular choice for the next generation of throughput oriented architectures. We introduce a hardware technique called "diverge on miss" that allows SIMD cores to better tolerate memory latency for workloads with non-contiguous memory access patterns. Individual threads within a SIMD "warp" are allowed to slip behind other threads in the same warp, letting the warp continue execution even if a subset of threads are waiting on memory. Diverge on miss can either increase the performance of a given design by up to a factor of 3.14 for a single warp per core, or reduce the number of warps per core needed to sustain a given level of performance from 16 to 2 warps, reducing the area per core by 35%.

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Beating in-order stalls with "flea-flicker" two-pass pipelining

Cited by 29 publications

References 17 publications

Submitted to IEEE Transactions on Parallel and Distributed Systems Special Issue on CMP Architectures

Submitted to IEEE Transactions on Parallel and Distributed Systems Special Issue on CMP Architectures

Discerning the dominant out-of-order performance advantage

Increasing memory miss tolerance for SIMD cores

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