2015
DOI: 10.1016/j.nima.2014.12.011
|View full text |Cite
|
Sign up to set email alerts
|

Beam test performance of the SKIROC2 ASIC

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1
1
1

Citation Types

1
13
0

Year Published

2015
2015
2020
2020

Publication Types

Select...
5
2

Relationship

3
4

Authors

Journals

citations
Cited by 10 publications
(14 citation statements)
references
References 11 publications
1
13
0
Order By: Relevance
“…The VFE ASICs are 16 SKIROC2 [18,19,20] (Silicon pin Kalorimeter Integrated ReadOut Chip), that have been designed for the readout of silicon PIN diodes. The SKIROC2 are enclosed in an LFBGA package and are bump bonded to the PCB.…”
Section: The Siw-ecal Technological Prototypementioning
confidence: 99%
See 1 more Smart Citation
“…The VFE ASICs are 16 SKIROC2 [18,19,20] (Silicon pin Kalorimeter Integrated ReadOut Chip), that have been designed for the readout of silicon PIN diodes. The SKIROC2 are enclosed in an LFBGA package and are bump bonded to the PCB.…”
Section: The Siw-ecal Technological Prototypementioning
confidence: 99%
“…Earlier experience with the SKIROC2 ASIC has been reported in [19,20,21]. For the following, the internal SKIROC2 parameters determined in these references are adopted except if otherwise stated.…”
Section: Commissioning Of the Detectormentioning
confidence: 99%
“…The bias voltage needed for the sensor depletion is provided through a conductive foil of copper and kapton glued to the back of the sensor and connected to the high voltage through the interface card or the SL-Board (see Section III). All previous published results of the technological prototype of the SiW-ECAL [10], [13] have been obtained with ASUs equipped with ASICs in different plastic/ceramic packagings. That generation of ASUs is called as FEV.…”
Section: Active Signal Unit (Asu)mentioning
confidence: 99%
“…The boards have a thickness of 3.2-3.5 mm including components and connectors. Until now, the digital readout of the FEVs was realised with a Detector Interface Card (DIF) interfaced with an small adapter card (SMB) for signal buffering and power regulation which is placed between DIF and the ASUs (see [10], [13]). The FEV13 design included two conceptual modifications with respect the previous FEV: the addition of two new layers (12 in total) including one extra layer to separate the analogue and digital power supply layers of the ASIC and a modification on the ASU conectivity.…”
Section: Active Signal Unit (Asu)mentioning
confidence: 99%
“…For the readout of the SiPMs a version of the HGCROC, including a capacitive charge divider, will be produced. HGCROC is based on the SKIROC2 chip [5] for the CALICE collaboration [6]. A development version named SKIROC2_CMS, optimized for the CMS testbeam, shows encouraging results [7].…”
Section: Front-end Electronics Requirements and Architecturementioning
confidence: 99%