BDD-based logic synthesis for LUT-based FPGAs

Abstract

Contemporary FPGA synthesis is a multiphase process that involves technology-independent logic optimization followed by FPGA-specific mapping to a target FPGA technology. Conventional technology-independent transformations target standard cells and are unable to optimize circuits with constraints and goals specific to FPGA architectures. This article describes an FPGA-specific logic synthesis approach, which unites multilevel logic transformation, decomposition, and optimization techniques into a single synthesis framework. This system performs network transformation, decomposition, and optimization at an early stage to generate a network that can be directly mapped onto FPGAs. Our techniques are built upon a BDD-based logic decomposition system. With this system, both AND-OR decompositions and AND-XOR decompositions can be identified, resulting in large area savings for synthesized XOR-intensive circuits. To induce good decompositions, a maximum fanout free cone (MFFC) -based partial clustering and collapsing technique is used. This step is followed by an area-minimizing variable partitioning heuristic that decomposes collapsed nodes into LUT-feasible subfunctions. As a postprocessing step, a performance-driven resynthesis phase is performed to alleviate increased delay caused by excessive logic sharing. We compare the quality of results obtained using our techniques with those of academic (BoolMap, SIS) and industry (Altera Quartus) FPGA synthesis tools. Experimental results indicate that the circuits generated by our techniques are not only smaller, but are also significantly faster than those synthesized by conventional FPGA synthesis tools. Furthermore, the computation times required by our techniques are significantly smaller than those of previous techniques.

Functionally linear decomposition and synthesis of logic circuits for FPGAs

“…In this section we present area, depth and compilation time results and contrast them with two academic synthesis systems: ABC [15] which utilizes structural transformations, and BDS-PGA 2.0 [6] that performs BDD based boolean optimizations.…”

“…Our results show that in comparison to state-of-the-art synthesis tools [6][15], our approach produces better results on average for XOR-based logic circuits, using little processing time.…”

“…Recently, XOR based decompositions were addressed by using Davio expansions [10] and with the help of BDDs [5,6]. With Davio expansions Reed-Muller logic equation can be generated for a function, utilizing XOR gates.…”

Area–Oriented Technology Mapping for LUT–Based Logic Blocks

“…The essence of using BDDs in the process of synthesis dedicated to FPGA structures has been presented by Scholl (2001). In a BDS PGA system using BDDs, resynthesis occurs (Vemuri et al, 2002).…”

Efficient SAT-based Boolean matching for FPGA technology mapping

“…Depending on the technology mapping approach, the resulting network can exhibit different area, delay, and power costs. Today, much interest is placed in developing technology mapping techniques that minimize combinations of these optimization factors [1], [2], [3], [4].…”