Bayesian Optimization for Efficient Accelerator Synthesis

Mehrabi, Atefeh; Manocha, Aninda; Lee, Benjamin C.; Sorin, Daniel J.

doi:10.1145/3427377

Cited by 11 publications

(13 citation statements)

References 77 publications

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“…Prospector [12] uses Bayesian optimization that builds a probabilistic model of the design space and iteratively determines the best points to sample. ProspectorâĂŹs Bayesian Optimization Unit uses a squared exponential kernel as a Gaussian process to create a model of the design space.…”

Section: Related Workmentioning

confidence: 99%

Sherlock: A Multi-Objective Design Space Exploration Framework

Gautier

Althoff²,

Crutchfield

et al. 2022

ACM Trans. Des. Autom. Electron. Syst.

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Design space exploration (DSE) provides intelligent methods to tune the large number of optimization parameters present in modern FPGA high-level synthesis (HLS) tools. HLS parameter tuning is a time-consuming process due to lengthy hardware compilation times – synthesizing an FPGA design can take tens of hours. DSE helps find an optimal solution faster than brute-force methods without relying on designer intuition to achieve high-quality results. Sherlock is a DSE framework that can handle multiple conflicting optimization objectives and aggressively focuses on finding Pareto optimal solutions. Sherlock integrates a model selection process to choose the regression model that helps reach the optimal solution faster. Sherlock designs a strategy based around the Multi-Armed Bandit (MAB) problem, opting to balance exploration and exploitation based on the learned and expected results. Sherlock can decrease the importance of models that do not provide correct estimates, reaching the optimal design faster. Sherlock is capable of tailoring its choice of regression models to the problem at hand, leading to a model that best reflects the application design space. We have tested the framework on a large dataset of FPGA design problems and found that Sherlock converges toward the set of optimal designs faster than similar frameworks.

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Section: Related Workmentioning

confidence: 99%

Sherlock: A Multi-Objective Design Space Exploration Framework

Gautier

Althoff²,

Crutchfield

et al. 2022

ACM Trans. Des. Autom. Electron. Syst.

View full text Add to dashboard Cite

show abstract

“…They estimate the resources and performance of each point in the design space. Model-free techniques include approaches in which the HLS tool is treated as a black box, such as Bayesian optimization and reinforcement learning techniques [112], [113], [114], [115].…”

Section: B Fpga-based Design Space Explorationmentioning

confidence: 99%

“…Other models focus on the DSE process are presented in [126], [127], [128], and [129]. [114], which uses Bayesian techniques to obtain the best configurations FIGURE 9. A DSE methodology presented in [116], [118].…”

Section: ) Modelsmentioning

confidence: 99%

High-Level Synthesis Hardware Design for FPGA-Based Accelerators: Models, Methodologies, and Frameworks

et al. 2022

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Hardware accelerators based on field programmable gate array (FPGA) and system on chip (SoC) devices have gained attention in recent years. One of the main reasons is that these devices contain reconfigurable logic, which makes them feasible for boosting the performance of applications. High-level synthesis (HLS) tools facilitate the creation of FPGA code from a high level of abstraction using different directives to obtain an optimized hardware design based on performance metrics. However, the complexity of the design space depends on different factors such as the number of directives used in the source code, the available resources in the device, and the clock frequency. Design space exploration (DSE) techniques comprise the evaluation of multiple implementations with different combinations of directives to obtain a design with a good compromise between different metrics. This paper presents a survey of models, methodologies, and frameworks proposed for metric estimation, FPGA-based DSE, and power consumption estimation on FPGA/SoC. The main features, limitations, and trade-offs of these approaches are described. We also present the integration of existing models and frameworks in diverse research areas and identify the different challenges to be addressed. INDEX TERMSComputing models, design space exploration, field programmable gate array (FPGA), system on chip (SoC), power consumption.years (2016-2022) and have been selected based on the topics addressed in this survey. Several papers published before 2016 have been considered because of their contributions to the current literature. C. OUTLINEThe remainder of this paper is organized as follows. Section II briefly presents the most widely used parallel computing models for CPU, GPU, and multicore processors. Section III introduces the FPGA-based reconfigurable hardware accelerator architectures, hardware/software co-design, DSE and metrics, and the techniques to improve latency, area, and power for this technology. In Section IV, we describe previous works on models, methodologies, and frameworks proposed for FPGA/SoC according to their main features: metrics estimation (IV-A), FPGA-based DSE (IV-B), and power consumption estimation (IV-C); and in Section IV-D, we present a summary and discussion. The integration of models and frameworks for FPGA-based reconfigurable hardware accelerators in different research fields is exposed in Section V. Challenges are analyzed in Section VI. Finally, conclusions are presented in Section VII. II. PARALLEL COMPUTING MODELS FOR PERFORMANCE ESTIMATIONComputing models allow to easily analyzing algorithms by simplifying the computational world to a reduced set of parameters that define the cost of arithmetic and memory access operations and communication. These models contribute to the search for efficient algorithms for a given architecture, improving the productivity of designers, programmers, and engineers. A small amount of communication, a small number of operations, and a high degree of parallelism are key points that d...

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“…Furthermore, BO can estimate a surrogate model of the system that helps to explain the inter-dependencies of design variables. For instance, in [8], the authors suggested a framework for designspace exploration for C/C++ High-Level Synthesis that uses BO. They have shown that BO outperforms the traditional search method in terms of latency and resource usage in the FPGA targets.…”

Section: Related Workmentioning

confidence: 99%

“…Although the approach we are presenting also uses BO to perform design-space exploration, there are two distinct features that differentiate our work from [3], [8]. First, our work is based on High-Level Synthesis for OpenCL kernels.…”

Section: Related Workmentioning

confidence: 99%

Efficient Design Space Exploration of OpenCL Kernels for FPGA Targets Using Black Box Optimization

Ghaffari

Savaria

2021

IEEE Access

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Nowadays, many industries are in favor of using intelligent design-space exploration as opposed to brute-force analysis. In many applications, the design-space is defined by multiple variables and their interactions. Although brute-force analysis is very simple, it is rarely scalable when the number of variables in the system increases. With the rising complexity of hardware designs, more intelligent approaches are needed to explore the design options. This paper proposes using smart meta-heuristic search algorithms such as Grey Wolf Optimization (GWO) in conjunction with Bayesian Optimization (BO) to solve this problem. We show that we can further reduce the design effort using a surrogate model that is created based on a novel hybrid GWO-BO method. The surrogate model is a useful abstraction to detect functional and physical inter-dependencies in the system in order to accurately predict its performance (e.g. throughput or latency). We evaluate our methodology and show that it can produce competitive results in order to find the best design variables that maximize performance of the system. Finally, we compare our results with previous statistical and heuristic methods proposed in the literature and find that the proposed GWO-BO method always performs better than the other considered methods.

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Bayesian Optimization for Efficient Accelerator Synthesis

Cited by 11 publications

References 77 publications

Sherlock: A Multi-Objective Design Space Exploration Framework

Sherlock: A Multi-Objective Design Space Exploration Framework

High-Level Synthesis Hardware Design for FPGA-Based Accelerators: Models, Methodologies, and Frameworks

Efficient Design Space Exploration of OpenCL Kernels for FPGA Targets Using Black Box Optimization

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