Basic characteristics of metal-ferroelectric-insulator-semiconductor structure using a high-k PrOx insulator layer

Abstract

Articles you may be interested inMetal-ferroelectric ( BiFeO 3 ) -insulator ( Y 2 O 3 ) -semiconductor capacitors and field effect transistors for nonvolatile memory applications Effect of bismuth oxide as a buffer layer on metal-lanthanum-substituted bismuth titanate-insulator-semiconductor structures

Electrical properties of (Bi,La)4Ti3O12-based ferroelectric-gated field effect transistors employed with a thermally oxidized SiO2 layer

“…[16][17][18] These values will yield promising retention characteristics but studies on the leakage current must be considered first. 19 Fig. 5 shows the I-V characteristics measured at room temperature for the MFIS-diodes with a sweep rate of 0.2 V/s at positively and negatively increasing voltages.…”

Influence of the ferroelectric–electrode interface on the characteristics of MFIS-FETs

“…Metal-ferroelectric-insulator-semiconductor field-effect transistor (MFIS-FET) has been considered as candidate for practical use in FET-type nonvolatile memories because of its significant advantage over the 1T1C and 2T2C, including low power consumption, nondestructive readout operation, and good scalability [1][2][3][4][5]. In order to optimize the design and the fabrication parameters of MFIS-FET, Miller and McWhorter studied the operational properties theoretically based on Brews' sheet model and a mathematical model [1].…”

Integration of lead-free ferroelectric on HfO2/Si (100) for high performance non-volatile memory applications

“…Ferroelectric integration on closely lattice mismatched NdGaO 3 or SrTiO 3 substrates is an alternative approach towards fabrication of electronic devices, however, these substrates cannot be embedded into complementary metal-oxide-semiconductor (CMOS) systems for further device processing since current CMOS processing technologies are based on low-cost, large area Si5. Many researchers have attempted to implement the ferroelectric materials onto Si, but direct integration results in cross-diffusion that creates defect states and degrades the electrical transport properties34678910111213. Moreover, an interfacial reaction between the ferroelectric layer and the Si can provide poor charge retention property which ultimately hinders the device performance.…”

“…Moreover, an interfacial reaction between the ferroelectric layer and the Si can provide poor charge retention property which ultimately hinders the device performance. To alleviate these problems, a high-k barrier layer was introduced by several researchers between the ferroelectric and the Si substrate34678910111213. The limitations of this approach are the presence of depolarization field across the ferroelectric layer and the large voltage drop across the oxide layer, which results in a poor device performance and also increases the device operation voltage13.…”

“…It is noteworthy to mention that the performance of such memory devices can be emphasized by investigating the three important parameters; memory window (MW), leakage current, and charge retention time. Although, many researchers have investigated the ferroelectric based NVM devices onto Si platform, but not much work has been performed in elucidating the correlation between the domain nucleation and growth in ferroelectric films for NVM device and switching hysteresis34678910111213. It is important to quantify the behavior of domains and perform switching measurements in order to explain the macroscale electrical properties21718.…”