Basal Plane Dislocation Free Recombination Layers on Low-Doped Buffer Layer for Power Devices

Abstract

We report a novel approach to grow BPD-free 4H-SiC device-ready epilayers, where we start by growing a thin low-doped buffer layer (5 × 1015 to 1 × 1016 cm–3, N-type) to achieve 100% BPD conversion, followed by a moderately thick (∼10 μm) higher-doped recombination layer (5 × 1016 to 1.6 × 1017 cm–3, N-type) to ensure that all recombination occurs within a BPD-free region. High doping of the BPD-free recombination layer ensures fast carrier recombination under forward bias, preventing any stacking fault nucleation in the active layer during bipolar device operation. All the individual BPDs in the buffer epilayer are converted to benign threading edge dislocations (TEDs) over a wide range of C/Si ratios (1 to 1.8), introducing a minimal on-resistance of <0.5 mΩ-cm2. 100% BPD conversion occurs due to the controlled and highly anisotropic eutectic etching of the buffer layer which produces narrow sector angle (5°) for the BPD etch pits to enable conversion of the BPDs within ∼1.5 μm of epilayer growth into TEDs, by promoting lateral growth at the narrow sector of BPD etch pits. This technique enables the translation of BPD conversion technology to real high-power bipolar device architectures in applications such as electric vehicles and solar power grid compatibility circuitry.

Reaction pathway analysis for the conversion of perfect screw basal plane dislocation to threading edge dislocation in 4H-SiC

“…[9][10][11] Since unconverted BPDs propagate into the epitaxial layer, [12][13][14] many researchers have investigated increases in BPD-TED conversion ratios. For instance, the following methods have been proposed to increase the conversion ratio: the formation of etch pits using a chemical solution prior to epitaxy, [15][16][17][18][19][20] the formation of a surface pattern using plasma etching prior to epitaxy, 21) the interruption of epitaxial growth, 22,23) the use of H 2 etching, 24) the increase of the C/Si ratio, 25) the increase of the growth rate, 26,27) the reduction of the off-cut angle of the substrate, 25,28) the use of chemical mechanical polishing (CMP) to obtain a flat substrate surface, 26) and the use of thermal annealing. 29) However, since the BPD-TED conversion rate still has not reached 100% with any of these methods, further studies are required.…”

Review on Power Cycling Reliability of SiC Power Device

“…Balachandran found that, in power cycling operations, the milliamp-level currents adopted for junction temperature measurements do not trigger the degradation of SiC body diodes compared to load currents. And, with the improvement of SiC's manufacturing processes, the phenomenon of degradation and consumption due to packaging in SiC body diodes is no longer significant [71]. Another phenomenon is that, when the applied voltage drop on the gate of DUT is less than −4 V, the voltage drop generated by the test current flowing through the body diode has been proven to be a reliable temperature-sensitive parameter.…”

Dislocations in 4H silicon carbide

“…Therefore, various efforts have been dedicated to convert BPDs to TEDs during the homoepitaxy of 4H-SiC, to enhance the reliability of 4H-SiC based bipolar devices. It has been found that increasing the growth rate, inserting a N-doped buffer layer, and high-temperature growth interruptions are beneficial for increasing the conversion ratio of BPDs [101][102][103]. The pre-growth treatment of 4H-SiC substrates, such as optimizing the cleaning procedure, molten-alkali etching and lithographic patterning, also promotes the conversion of BPDs to TEDs [104][105][106].…”