Bandwidth Compression of Floating-Point Numerical Data Streams for FPGA-Based High-Performance Computing

Abstract

Although computational performance is often limited by insufficient bandwidth to/from an external memory, it is not easy to physically increase off-chip memory bandwidth. In this study, we propose a hardware-based bandwidth compression technique that can be applied to field-programmable gate array-- (FPGA) based high-performance computation with a logically wider effective memory bandwidth. Our proposed hardware approach can boost the performance of FPGA-based stream computations by applying a data compression technique to effectively transfer more data streams. To apply this data compression technique to bandwidth compression via hardware, several requirements must first be satisfied, including an acceptable level of compression performance and a sufficiently small hardware footprint. Our proposed hardware-based bandwidth compressor utilizes an efficient prediction-based data compression algorithm. Moreover, we propose a multichannel serializer and deserializer that enable applications to use multiple channels of computational data with the bandwidth compression. The serializer encodes compressed data blocks of multiple channels into a data stream, which is efficiently written to an external memory. Based on preliminary evaluation, we define an encoding format considering both high compression ratio and small hardware area. As a result, we demonstrate that our area saving bandwidth compressor increases performance of an FPGA-based fluid dynamics simulation by deploying more processing elements to exploit spatial parallelism with the enhanced memory bandwidth.

The Case for Error-Bounded Lossy Floating-Point Data Compression on Interconnection Networks

“…The essential idea of SZ is to use linear predictive coding for predictable data and to perform complicated binary analysis for unpredictable data. Another work [1] presented a similar idea of floating-point data compression for FPGA-based high-performance computing by using a one-dimensional polynomial predictor. The above lossy compression algorithms usually have a tradeoff between the compression latency overhead and the compression ratio.…”

“…We choose the arithmetic-based algorithmic approach because our target is IEEE 754 (single-and double-precision) floating-point formats with almost no bit-level locality for expressing two similar values. Although the arithmetic-based prediction requires buffer memory to retain previous inputs, the size of the buffer can be reduced by employing one-dimensional polynomial predictions [1].…”

“…A way to virtually increase the network bandwidth is the reduction of redundancy of communication data themselves. Some parallel scientific applications repeatedly generate similar communication data [1]. For this kind of communication, each compute node has a chance to reduce traffic by compressing communication data, e.g., by sending only the information of difference from the prior data.…”

An FPGA-Based Change-Point Detection for 10Gbps Packet Stream

“…In a paper [15], an FPGA-based FFT processing for variable length and multiple streams is proposed by using this method. In a paper [16], a compression mechanism for floating-point numerical data streams is proposed by using FPGA. In these cases, multiple instances are introduced to handle multiple streams.…”

High speed numerical integration algorithm using FPGA

“…They have proved that between the three implementations of Jacobi algorithm for matrix, the FPGA design gives the best task performance but the GPU had a superior scalability, while CPU was a poor computing platform. A systolic array structure was designed to support various matrix sizes on the FPGA implementation and thus, gives the best computing performance of matrices compared the other two [9][10].…”