Bandwidth-Aware Dynamic Prefetch Configuration for IBM POWER8

Navarro, Carlos; Feliu, Josué; Petit, Salvador; Gomez, Maria E.; Sahuquillo, Julio

doi:10.1109/tpds.2020.2982392

Cited by 8 publications

(10 citation statements)

References 27 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Some recent research [12], [13], [14], [15], [19], [20] has focused on heuristic-based solutions with the aim of achieving the best performance from the prefetching capabilities of commercial machines. All these works focus on IBM POWER processors, whose prefetcher is much more powerful and complex, and further performance gains are expected.…”

Section: Heuristic Based Solutionsmentioning

confidence: 99%

“…Recently, Navarro et al [15] consider different levels of aggressiveness and the inter-thread interference to propose a much more scalable and best performing approach for the IBM POWER8. All these works require exploration phases in order to check the performance of each studied configuration and select the best performing one.…”

Section: Heuristic Based Solutionsmentioning

confidence: 99%

“…Recent work [17], [12], [15] found that depth and urgency are the fields that impact on performance the most The former configures the level of the prefetch depth and is related to the number of cache lines that are brought into the on-chip caches. Urgency indicates how quickly this depth can be reached.…”

Section: The Ibm Power8 Prefetch Enginementioning

confidence: 99%

“…Recent research has focused on dynamically selecting the best prefetch configuration for the running workload at run-time. Some works have concentrated on parallel workloads [12], [13], [14] and other approaches target multi-program single-threaded workloads [15] which is particularly complex because each application has different memory characteristics and prefetch requirements.…”

Section: Introductionmentioning

confidence: 99%

“…The second, multi-core network, also takes into account the inter-thread interference at the shared resources among corunning applications. More precisely, it considers the memory bandwidth consumed by the co-runners, shown recently as the main critical shared resource for prefetching in the IBM POWER8 [15]. This paper makes three main contributions:…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

DeepP: Deep Learning Multi-Program Prefetch Configuration for the IBM POWER 8

Lurbe¹,

Feliu

Petit³

et al. 2022

IEEE Trans. Comput.

Self Cite

View full text Add to dashboard Cite

Current multi-core processors implement sophisticated hardware prefetchers, that can be configured by application (PID), to improve the system performance. When running multiple applications, each application can present different prefetch requirements, hence different configurations can be used. Setting the optimal prefetch configuration for each application is a complex task since it does not only depend on the application characteristics but also on the interference at the shared memory resources (e.g. memory bandwidth). In his paper, we propose DeepP, a deep learning approach for the IBM POWER8 that identifies at run-time the best prefetch configuration for each application in a workload. To this end, the neural network predicts the performance of each application under the studied prefetch configurations by using a set of performance events. The prediction accuracy of the network is improved thanks to a dynamic training methodology that allows learning the impact of dynamic changes of the prefetch configuration on performance. At run-time, the devised network infers the best prefetch configuration for each application and adjusts it dynamically. Experimental results show that the proposed approach improves performance, on average, by 5,8%, 6,7%, and 15,8% compared to the default prefetch configuration across different 6-, 8-, and 10-application workloads, respectively.

show abstract

Section: Heuristic Based Solutionsmentioning

confidence: 99%

Section: Heuristic Based Solutionsmentioning

confidence: 99%

Section: The Ibm Power8 Prefetch Enginementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

DeepP: Deep Learning Multi-Program Prefetch Configuration for the IBM POWER 8

Lurbe¹,

Feliu

Petit³

et al. 2022

IEEE Trans. Comput.

Self Cite

View full text Add to dashboard Cite

show abstract

RL-CoPref: a reinforcement learning-based coordinated prefetching controller for multiple prefetchers

Yang,

Fang,

et al. 2024

J Supercomput

View full text Add to dashboard Cite

Modern processors employ data prefetchers to alleviate the impact of long memory access latency. However, current prefetchers are designed for specific memory access patterns, which perform poorly on mixed applications with multiple memory access patterns. To address these issues, RL-CoPref, a reinforcement learning (RL)-based coordinated prefetching controller for multiple prefetchers, is proposed in this paper. RL-CoPref takes diverse program context information as the input, learns to maximize cumulative rewards, and evaluates prefetch quality based on prefetch hits/misses and memory bandwidth utilization. It can dynamically adjust the prefetch activation and prefetch degree, enabling multiple prefetchers to complement each other on mixed applications. Our extensive evaluation, utilizing the ChampSim simulator, demonstrates that RL-CoPref can effectively adapt to various workloads and system configurations, optimizing prefetch control. On average, RL-CoPref achieves 76.15% prefetch coverage, having 35.50% IPC improvement, outperforming state-of-the-art individual prefetchers by 5.91–16.54% and outperforming SBP, a state-of-the-art (non-RL) prefetch controller, by 4.64%.

show abstract