Bandpass-Type NGD Design Engineering and Uncertainty Analysis of RLC-Series Resonator Based Passive Cell

Boussougou, Yves Constant Mombo; Sambatra, Eric Jean Roy; Jaomiary, Antonio; Ramifidisoa, Lucius; Murad, Nour; Kouadio, Jean-Paterne; Ngoho, Samuel; Sahoa, Frank Elliot; Baccar, Sahbi; Randriatsiferana, Rivo

doi:10.2528/pierc22011705

Cited by 2 publications

(1 citation statement)

References 49 publications

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“…Some of them have attempted to implement NGD circuits. Work carried out with microchip printed circuits can be found in [20], [21], designed with CMOS technology in [22], [23], and AOP with RLC-lumped in [24]- [26]. They demonstrate that the development of NGD circuits is still an uncommon practice and remains a challenge.…”

Section: ) Remarks and Discusionsmentioning

confidence: 99%

Novel Digital NGD Methodology for FPGA-Based Embedded Systems

Randriatsiferana,

Lorandel,

Salvador

et al. 2024

IEEE Access

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Negative Group Delay (NGD) is a concept not widely explored in embedded digital signal processing systems, and this study aims to fill this gap. It presents a novel methodology for implementing NGD using second-order Finite Impulse Response (FIR) filter. We include synthesis results that prove the viability of using FIR filters for NGD functions under specific conditions, which involve considering asymmetry coefficients in the time domain. The synthesized results demonstrate the desired time-advance values relative to the input signal frequency, and it is observed that as the normalized advanced-time increases, the normalized frequency also increases. We then design, simulate and test FIR-based NGD parameters before building an FPGA-based proof-of-concept implementation for embedded systems. The experimental results show how the frequency responses of the NGD function at baseband frequency correlate well with the theoretical hypothesis, supporting our analysis and validating our methodology. The NGD principle presented in this paper is potentially useful for group delay correction processes and signal pure delay reduction in embedded digital signal processing systems.

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Section: ) Remarks and Discusionsmentioning

confidence: 99%

Novel Digital NGD Methodology for FPGA-Based Embedded Systems

Randriatsiferana,

Lorandel,

Salvador

et al. 2024

IEEE Access

Self Cite

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Positive‐to‐negative tunable delay circuit designed with NGD RC network

Junwen,

Junyan,

Silochi

et al. 2024

Circuit Theory & Apps

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SummaryDespite the performed progressive research work, the interpretation of the negative group delay (NGD) function remains not familiar to non‐specialist design and fabrication circuit engineers. The functionality misunderstanding limits the NGD circuit applications compared to other classical electronic functions. The present paper deals with the design of a tunable circuit by operating with positive and negative delay behaviors. The topology of the tunable circuit by using a low‐pass (LP) type NGD circuit is described. The design formulas for calculating the circuit resistor and capacitor parameters from the desired delay are expressed. The design feasibility of the tunable circuit composed of LP‐NGD cell and RC‐circuit is validated with a proof‐of‐concept (PoC) implemented on a test board. Two different signals with pulse and arbitrary waveforms having tens‐milliseconds duration were considered during the validation tests. As expected by tuning a varistor from 0.4 kΩ to 1 kΩ, the negative delay behavior varying from about −0.4 ms was verified thanks to the time‐advanced effect due to the LP‐NGD property. Then, the output signal delay was observed to become positive when the varistor was tuned from 1 kΩ to 3 kΩ.

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Bandpass-Type NGD Design Engineering and Uncertainty Analysis of RLC-Series Resonator Based Passive Cell

Cited by 2 publications

References 49 publications

Novel Digital NGD Methodology for FPGA-Based Embedded Systems

Novel Digital NGD Methodology for FPGA-Based Embedded Systems

Positive‐to‐negative tunable delay circuit designed with NGD RC network

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