Backside Flip-Chip testing by means of high-bandwidth luminescence detection

Tosi, Alberto; Stellari, Franco; Zappa, Franco; Cova, S.

doi:10.1016/s0026-2714(03)00302-0

Cited by 3 publications

(1 citation statement)

References 14 publications

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“…Nowadays, multiple metal layers and dense back-end-of-the-line (BEOL) structures prevent optical testing from the front side of integrated circuits, and impose the testing only from the backside of the chip (Fig. 1), where optical access to MOS transistors is possible [9]. Since the silicon absorption is high, especially for wavelengths shorter than 1.1 and for highly-doped substrates [10], it is necessary to thin the substrate of the chip in order to lower the silicon absorption [11].…”

Section: Introductionmentioning

confidence: 99%

A Packaging Solution for Optically Testing Wire-Bonded Chips

Tosi

Stellari

Zappa

et al. 2008

IEEE Trans. Adv. Packag.

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In this paper, we describe the design and the experimental characterization of a packaging technique for backside optical testing of chips requiring wirebonding. Optical testing methods, based either on the collection of spontaneous hot-carrier photoemission or on laser stimulation, require an optical access to the active area of the circuit through the backside of the chip, while still providing mechanical support to the thinned die (very fragile), heat sinking capability, power and electrical signals. The proposed package fulfils all these requirements and it can hence be used for picosecond imaging for circuit analysis/time resolved emission measurements, emission microscopy investigations, laser voltage probe, thermal laser stimulation, photoelectric laser stimulation, and other failure analysis methods that require optical access to the transistor level through the silicon backside. The advantages of the new package are its versatility (it can fit different chip sizes), easy handling, low cost, and the fact that it is designed for optical testing and not just for electrical testing. We successfully used the proposed package for optically test chips in advanced complementary metal-oxide-semiconductor technologies (65 nm): measurements at low voltage are possible thanks to the proposed package.Index Terms-Complementary metal-oxide-semiconductor (CMOS), emission, laser, metal-oxide-semiconductor field-effect transistor (MOSFET), optical testing, package, photoemission, picosecond imaging for circuit analysis (PICA), testing, time resolved emission (TRE).

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Section: Introductionmentioning

confidence: 99%