Backside De-Processing of Integrated Circuits 40 nm and Below

Abstract

This paper presents a novel backside de-processing technique for effective failure analysis of advanced multi-level interconnect metallization CMOS ICs with flip chip package.

Backside EBIRCH Defect Localization for Advanced Flip Chip Failure Analysis

“…For instance, nanoprobing or ebeam absorbed current (EBAC) may not be able to capture a resistive via interface from the front side as only one side of the via is accessible by probing. To address these challenges, different approaches was developed for defect localization, including approaching from backside of die [1] [2].…”