B/W adaptive image grabber with analog motion vector estimator at 0.3 GOPS

Tomasini, A.; Brattoli, M.; Chioffi, E.; Colli, G.; Gerna, D.; Pasotti, M.

doi:10.1109/isscc.1996.488528

Cited by 16 publications

(13 citation statements)

References 3 publications

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“…Since in finding the best motion vectors most of the processing time is taken loading pixels into memory, it can be shown that the proposed serial-parallel 1 architecture performs at about 70% of the operating speed of fully-parallel architectures [8], [12], [13]. The latter are many more times complicated than necessary for ME, an issue which was overlooked in [8].…”

Section: Architecturementioning

confidence: 99%

“…The latter are many more times complicated than necessary for ME, an issue which was overlooked in [8]. Hence, the efficient architecture in this work results in large savings in power consumption and size (see comparison in Section IV).…”

Section: Architecturementioning

confidence: 99%

“…To address this, analog circuits have been proposed as a low-power alternative for realizing the ES-BMA [8], [9]. In this brief, a novel mixed-signal approach featuring pixel reuse is adopted for the design of a proof-of-concept ME processor using the ES-BMA.…”

Section: Introductionmentioning

confidence: 99%

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Motion estimation processor using mixed-signal approach

Panovic¹,

Demosthenous²

2006

IEEE Trans. Circuits Syst. II

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This paper describes the design, realization, and evaluation of a mixed-signal motion estimation processor using the full-search block-matching algorithm. The approach features digital I/O and a low-power, compact analog computational core. The proof-of-concept realization whose architecture incorporates pixel reuse, was fabricated in 0.8-m CMOS technology occupying 0.65 mm 2 , and operates on 4 4 pixel blocks and a search area of 8 8 pixels. The processor achieves a low energy consumption per motion vector of 1.35 nJ and dissipates 0.8 mW from a 3-V power supply at QCIF 15 frames/s. The approach is intended for portable applications of digital video encoding.

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Section: Architecturementioning

confidence: 99%

Section: Architecturementioning

confidence: 99%

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Motion estimation processor using mixed-signal approach

Panovic¹,

Demosthenous²

2006

IEEE Trans. Circuits Syst. II

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“…An example of weight regularity which allows implementation on a weight-routed array is interframe block-matching [13,14,15], where the weights on one row are a shifted version of the weights of the row before ( fig. 11).…”

Section: 4: Weight-stored and Weight-routed Arraysmentioning

confidence: 99%

“…Blockmatching is an algorithm for computing relative image frame motion by matching a block of pixels in the current frame to the best location among a finite set of possible locations within a "search window" of the previous frame [13,14]. Our computing array has been implemented with a CMOS camera and analog frame buffers on a powerful analog smart sensor [15], though the discussion here will focus only on the core of the computing array.…”

Section: : Euclidean-squared Computing Arraymentioning

confidence: 99%

Array-based analog computation: principles, advantages and limitations

Krämer

Proceedings of Fifth International Conference on Microelectronics for Neural Networks

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Analog implementations of Neural Networks and other computing architectures have gained increasing interest over the last decade.The field is at a critical juncture: continued interest will depend on the ability to demonstrate a clear advantage over digital solutions to problems of commercial interest. The Neural Network Design Group at SGS-Thomson Microelectronics has been working to explore the advantages and limitations of analog computation and implementations of Neural Network architectures. We are investigating 3 large-scale analog VLSI chips, all of which work on problems in image processing. The use of analog computing arrays, because oftheir efficiency and regularity, have formed the basis of most of our designs, while several different computing modes, including current, charge, and conductance have been explored. Another area in which we have focused is on the use of floating-gate Flash-EEPROM devices for both non-volatile analog storage and computation. This paper will share insights into the lessons we have learned, the results we have achieved, and the limitations we have encountered. Particular emphasis will be made on two subjects: computational efficiency and equivalent precision of array-based analog computing circuits.

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