B-DTNMOS: a novel bulk dynamic threshold NMOS scheme

Elgharbawy, W.; Bayoumi, Magdy

doi:10.1109/iscas.2004.1329296

Cited by 6 publications

(3 citation statements)

References 5 publications

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“…One of the possible solutions is to implement a MOSFET with dynamic threshold voltage (V tb ). The dynamic threshold voltage MOSFET (DTMOS) circuit technology satisfies requirements of lowering the threshold voltage of a MOSFET and reducing stand-by current, both of which are necessary to obtain high performance at lower supply voltage in VLSI circuits (Assaderaghi et al, 1994;Assaderaghi, 2000;Elhgarbawy and Bayoumi, 2004). When body and gate of a MOSFET are tied together, this configuration is known as DTMOS as shown in Figure 1.…”

Section: Introductionmentioning

confidence: 99%

Low voltage four‐quadrant analog multiplier using dynamic threshold MOS transistors

Niranjan

Gupta

2009

Microelectronics International

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Purpose -Real-time multiplication of two analog signals is one of the most important operations in analogue signal processing. Driven by low-power and low-voltage requirements for integrated mixedsignal portable applications, the paper's aim is to propose a novel four-quadrant low-voltage analog multiplier using dynamic threshold MOS transistors (DTMOS). Design/methodology/approach -The SPICE simulations were performed with 0.25 mm technology parameters and results verify the performance of the circuit. The multiplier is simulated at low-supply voltage of^0.5 V. Findings -The proposed multiplier has high linearity and simple structure hence it is suitable for high-performance and low-power analog VLSI applications. Originality/value -A new low-voltage four quadrant analog multiplier using DTMOS circuit topology is presented in the paper.

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Section: Introductionmentioning

confidence: 99%

Low voltage four‐quadrant analog multiplier using dynamic threshold MOS transistors

Niranjan

Gupta

2009

Microelectronics International

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“…However, the TSPC logic contains PMOS which is not suitable in high speed circuits. [4] and [5] utilized the bulk dynamic threshold technique in domino-like dynamic logic. However, the bulk bias is driven by the clock signal such that the load of the clock is drastically increased.…”

Section: Introductionmentioning

confidence: 99%

Low-power 7.2 GHz complementary all-N-transistor logic using 90 nm CMOS technology

Hsu

Yao

Juan

et al. 2009

2009 IEEE International Symposium on Circuits and Systems

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This paper proposed an complementary all-Ntransistor (CANT) comprising ANT logic and inverted ANT logic. In ANT logic's N-Block, the threshold voltage of the transistors is variable depending on the operation of the entire logic block. In the evaluation phase, the bulk voltage of the transistors in the N-Block is increased to VDD − V thn to enhance the operation speed. In the pre-charge phase, the bulk voltage of the transistors in the N-Block is dropped to almost 0 V such that the subthreshold leakage current is reduced. By utilizing such a variable bulk voltage scheme in the proposed complementary ANT (CANT) logic, a 32-bit CLA is designed using TSMC 90 nm CMOS process to verify the low power and high speed performance. The area of the proposed design is 0.0483 mm 2 and the power dissipation is 102 mW given a 7.2 GHz clock at the worst PVT condition.

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“…6 Fig.f5r(B). erformnc ompnariso of body biain schemesi body-bicyasng canpbe foundg for acgiventsupply votagc and 10 mTMCtcnooyi shown in Figs.5()an 6B asrpre inr [12]. that strikes a balance between power consumption and progresses towards 20 nm and system constraints performance.…”

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confidence: 97%

Ultra-Low Voltage VLSI: Are We There Yet?

Ampadu

2006 IEEE International Symposium on Circuits and Systems

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Aggressively scaled supply voltage has been touted subthreshold) voltages to minimize energy consumption [5]. as one of the most powerful mechanisms for improving In these applications, energy efficiency typically overrides reliability and reducing power consumption in nanometer speed performance; therefore, the increased latencies technologies. Sophisticated adaptive power management generally associated with ultra-low voltage circuits do not techniques vary supply voltage from nominal to ultra-low pose a serious limitation. In applications requiring higher values to implement adaptive VLSI systems that gracefully performance, however, additional techniques must be used to respond to varying workload demands for improved energy restore the speed loss that accompanies voltage reduction. efficiency. Unfortunately, ultra-low voltage (sub-volt for These techniques are reviewed in Section II. Trends and current technologies) operation has been constrained by performance limitations. In this paper, the current state of pr oSectsor ultra-o voltage IV lus syte ar exmamy. low-voltage VLSI design is evaluated; techniques for n Secon III and Secon IV concludes wth a summar.maintaining acceptable throughputs at ultra-low voltages are reviewed; and trends and prospects for ultra-low voltage VLSI

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B-DTNMOS: a novel bulk dynamic threshold NMOS scheme

Cited by 6 publications

References 5 publications

Low voltage four‐quadrant analog multiplier using dynamic threshold MOS transistors

Low voltage four‐quadrant analog multiplier using dynamic threshold MOS transistors

Low-power 7.2 GHz complementary all-N-transistor logic using 90 nm CMOS technology

Ultra-Low Voltage VLSI: Are We There Yet?

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