AVPGEN-A test generator for architecture verification

Chandra, Ashok K.; Iyengar, V.; Jameson, David H.; Jawalekar, R.V.; Nair, Indira; Rosen, Barry K.; Mullen, M. P.; Yoon, J.-Y.; Armoni, Roy; Geist, Daniel; Wolfsthal, Yaron

doi:10.1109/92.386220

Cited by 61 publications

(29 citation statements)

References 9 publications

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“…Various solutions have been previously proposed to tackle the design verification problem [2,3,4,5]. Many of these solutions involve an automated test generator based on some form of pseudo random selection scheme to create test cases.…”

Section: Related Workmentioning

confidence: 99%

Using Genetic Evolutionary Software Application Testing to Verify a DSP SoC

Cheng

Lim

Sun³

et al. 2008

4th IEEE International Symposium on Electronic Design, Test and Applications (Delta 2008)

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IntroductionDesign verification of system-on-chips (SoCs) is expensive and time consuming. It accounts for up to 70% of resources in a typical design project [1]. Designing digital signal processor (DSP) SoCs create further verification complexities given the range of applications and end products DSPs are employed within.In order to test a DSP design more effectively, consideration must be given to how the DSP will be used and their intended applications. The eventual real-life usages of a DSP determine the particular design features and functions that are needed in the DSP. It is these design functionalities and their complexities that must be verified in-depth. Therefore, any effective verification strategy must incorporate extensive testing with application functions.To demonstrate this, the software application level verification methodology (SALVEM) [7,8] is employed to test the Tsinghua University Application Specific DSP (THUASDSP2004) [9]. The SALVEM technique was successfully used on other SoC previously [7,8]. The aim of this paper is to describe the application of SALVEM on a real world DSP SoC; thus demonstrate its feasibility and usefulness for DSP testing. Furthermore, for verification of the DSP, SALVEM is enhanced by an automated test generator that uses genetic evolutionary methods to create tests. The THUASDSP2004 DSP is an ideal candidate for SALVEM. It was designed specifically for multimedia applications and contains common DSP function blocks such as high performance mathematical and fast data transfer units, along with other specialized modules. These DSP architectural features are to be tested by SALVEM to enhance the design and verification quality of the DSP SoC.The reminder of this paper is as follows. Section 2 summarizes related work in design verification. Section 3 describes the DSP SoC design. The SALVEM verification approach and test generator are outlined in sections 4 and 5 respectively. Section 6 provides experimental results before the paper is concluded. Related WorkVarious solutions have been previously proposed to tackle the design verification problem [2,3,4,5]. Many of these solutions involve an automated test generator based on some form of pseudo random selection scheme to create test cases. The advantage with this approach is that many test cases can be created quickly with minimal effort. However, testing may not be optimized or effective. Due to the inherently random nature of such tests, similar functions may be repeatedly tested or other important test functions overlooked. Ideally, the tests generated should cover as much of the previously untested and critical design functions.Furthermore, hardware DSP designs require special verification considerations. Some DSP design and modeling environments like Matlab or Simulink do not describe the true hardware design implementation that will be eventually tape-out. They focus on high level DSP algorithmic validation, but the actual hardware design is not tested directly [10]

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Section: Related Workmentioning

confidence: 99%

Using Genetic Evolutionary Software Application Testing to Verify a DSP SoC

Cheng

Lim

Sun³

et al. 2008

4th IEEE International Symposium on Electronic Design, Test and Applications (Delta 2008)

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“…The third level of verification is done at the microprocessor level. A strong architectural-level instruction stream test-case generator, AVPGEN is used for the unit level as well as for the CP level [8]. Finally, system level verification is performed on symmetric multiprocessor (SMP) configurations.…”

Section: Fxu Verificationmentioning

confidence: 99%

The design of the fixed point unit for the z990 microprocessor

Busaba

Slegel

Carlough

et al. 2004

Proceedings of the 14th ACM Great Lakes Symposium on VLSI

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The paper presents the design of the Fixed Point Unit (FXU) for the IBM eServer z990 microprocessor (announced in 2Q '03) that runs at 1.2 GHz [2]. The FXU is capable of executing two Register-Memory instructions including arithmetic instructions and a branch instruction in a single cycle. The FXU executes a total of 369 instructions that operate on variable size operands (1 to 256 bytes). The instruction set include decimal arithmetic with multiplies and divides, binary arithmetic, shifts and rotates, loads/stores, branches, long moves, logical operations, convert instructions, and other special instructions. The FXU consists of 64-bit dataflow stack that is custom designed and a control stack that is synthesized. The current FXU is the first superscalar design for the CMOS z-series machines, has a new improved decimal unit, and has for the first time a 16x64 bit binary multiplier.

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“…Subsequently, it performs instruction assignment, global resource allocation, and condition setup to produce an assembly program ready for simulation [2].…”

Section: Theo: a Sophisticated Code Generatormentioning

confidence: 99%

“…State-of-the-art microprocessors, however, achieve high performance through several advanced execution mechanisms [5]. The increased complexity introduced by these mechanisms forces DVT teams to increasingly depend on advanced code generation tools for the functional verification of microprocessors [1,2,3,6].…”

Section: Introductionmentioning

confidence: 99%