Avoiding Shared Clocks in Networks of Timed Automata

Balaguer, Sandie; Chatain, Thomas

doi:10.2168/lmcs-9(4:13)2013

Cited by 2 publications

(1 citation statement)

References 28 publications

(29 reference statements)

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“…Those quasi-equal clocks are implicitly reduced by applying the sequential composition operator. The work in [13] avoids the use of shared clocks in single timed automaton by replacing shared clocks with fresh ones if the evolution of these automata does not depend on these clocks. This approach increments the number of clocks (in contrast to ours).…”

Section: Introductionmentioning

confidence: 99%

Quasi-Equal Clock Reduction: More Networks, More Queries

Herrera

Westphal

Podelski

2014

Tools and Algorithms for the Construction and Analysis of Systems

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Abstract. Quasi-equal clock reduction for networks of timed automata replaces equivalence classes of clocks which are equal except for unstable phases, i.e., points in time where these clocks differ on their valuation, by a single representative clock. An existing approach yields significant reductions of the overall verification time but is limited to so-called wellformed networks and local queries, i.e., queries which refer to a single timed automaton only. In this work we present two new transformations. The first, for networks of timed automata, summarises unstable phases without losing information under weaker well-formedness assumptions than needed by the existing approach. The second, for queries, now supports the full query language of Uppaal. We demonstrate that the cost of verifying non-local properties is much lower in transformed networks than in their original counterparts with quasi-equal clocks.

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Section: Introductionmentioning

confidence: 99%

Quasi-Equal Clock Reduction: More Networks, More Queries

Herrera

Westphal

Podelski

2014

Tools and Algorithms for the Construction and Analysis of Systems

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Automated Verification for Real-Time Systems

Song

Chin

2023

Tools and Algorithms for the Construction and Analysis of Systems

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The correctness of real-time systems depends both on the correct functionalities and the realtime constraints. To go beyond the existing Timed Automata based techniques, we propose a novel solution that integrates a modular Hoare-style forward verifier with a term rewriting system (TRS) on Timed Effects (TimEffs). The main purposes are to: increase the expressiveness, dynamically manipulate clocks, and efficiently solve clock constraints. We formally define a core language $$ C^{t} $$ C t , generalizing the real-time systems, modeled using mutable variables and timed behavioral patterns, such as delay, timeout, interrupt, deadline. Secondly, to capture real-time specifications, we introduce TimEffs, a new effects logic, that extends regular expressions with dependent values and arithmetic constraints. Thirdly, the forward verifier reasons temporal behaviors – expressed in TimEffs – of target $$ C^{t} $$ C t programs. Lastly, we present a purely algebraic TRS, i.e., an extended Antimirov algorithm, to efficiently check language inclusions between TimEffs. To demonstrate the feasibility of our proposal, we prototype the verification system; prove its soundness; report on case studies and experimental results.

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Avoiding Shared Clocks in Networks of Timed Automata

Cited by 2 publications

References 28 publications

Quasi-Equal Clock Reduction: More Networks, More Queries

Quasi-Equal Clock Reduction: More Networks, More Queries

Automated Verification for Real-Time Systems

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