AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems

Qureshi, Moinuddin K.; Kim, Dae-Hyun; Khan, Samira; Nair, Prashant J.; Mutlu, Onur

doi:10.1109/dsn.2015.58

Cited by 182 publications

(162 citation statements)

References 27 publications

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“…We also evaluate a baseline that completely skips 75% of refresh operations and optimistically assume that it requires no other operations or overheads; this baseline represents the best-case of all prior works that propose skipping refresh [8,25,32,41,42]. We refer to this baseline as Skipping Refresh.…”

Section: Baselinesmentioning

confidence: 99%

“…Many recent works propose skipping many refresh operations, by increasing refresh interval, to improve performance [8,25,32,35,41,42,43]. For example, RAIDR [35] profiles the charge retention time of DRAM cells in each row in memory and skips refresh operations to memory rows with long retention time.…”

Section: Skipping Refreshmentioning

confidence: 99%

“…Prior works have looked at how to reduce the performance impact due to memory refresh [8,13,25,32,35,39,40,41,42,43]. Some of them have explored intelligent refresh scheduling to block fewer pending read requests [13,39,40]; however, they provide limited effectiveness.…”

Section: Introductionmentioning

confidence: 99%

“…Some of them have explored intelligent refresh scheduling to block fewer pending read requests [13,39,40]; however, they provide limited effectiveness. As refresh latency increases, many later works have explored how to more aggressively address memory refresh performance overheads by skipping many required memory refresh operations [8,25,32,41,42] at the cost of reducing memory security and reliability [15,21,24,27,31]; however, this is inadequate for systems that do not wish to sacrifice security and reliability for performance.…”

Section: Introductionmentioning

confidence: 99%

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Nonblocking Memory Refresh

Nguyen

Lyu

Meng

et al. 2018

2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA)

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Since its inception half a century ago, DRAM has required dynamic/active refresh operations that block read requests and decrease performance. We propose refreshing DRAM in the background without stalling read accesses to refreshing memory blocks, similar to the static/background refresh in SRAM. Our proposed Nonblocking Refresh works by refreshing a portion of the data in a memory block at a time and uses redundant data, such as Reed-Solomon codes, in the block to compute the block's refreshing/unreadable data to satisfy read requests. For proof of concept, we apply Nonblocking Refresh to server memory systems, where every memory block already contains redundant data to provide hardware failure protection. In this context, Nonblocking Refresh can utilize server memory system's existing per-block redundant data in the common-case when there are no hardware faults to correct, without requiring any dedicated redundant data of its own. Our evaluations show that on average across five server memory systems with different redundancy and failure protection strengths, Nonblocking Refresh improves performance by 16.2% and 30.3% for 16gb and 32gb DRAM chips, respectively. Nonblocking Memory RefreshKate Vy H Nguyen (GENERAL AUDIENCE ABSTRACT)Main memory is an essential component of computers, which stores data being actively used. The dominant type of computer main memory is Dynamic Random Access Memory (DRAM). DRAM is divided into thousands of memory cells. Each cell stores a single bit of data as a charge on a capacitor. Charges may leak over time, causing the data stored to be lost. To maintain the data stored in memory, DRAM must periodically restore charges held by memory cells through an operation known as memory refresh. Refresh operations decrease system performance because they stall read requests to refreshing memory blocks.A memory block refers to the unit of data transferred per memory request. Conventional memory systems refresh all the data within the block at a time, therefore the entire memory block is inaccessible while it is being refreshed. Our proposed Nonblocking Refresh reduces the amount of data in a memory block which is inaccessible due to refresh by refreshing only a portion the memory block at a time. To satisfy read requests, the block's refreshing/inaccessible data is computed using redundant data. Nonblocking Refresh improves DRAM performance by refreshing DRAM in the background without stalling read accesses to refreshing memory blocks. For proof of concept, we apply Nonblocking Refresh to server memory systems, where every memory block already contains redundant data to provide hardware failure protection. In this context, Nonblocking Refresh can utilize server memory system's existing redundant data to improve performance, without adding additional redundancy overhead. Our evaluations show that on average across five server memory systems with different redundancy and failure protection strengths, Nonblocking Refresh improves performance by 16%-30%.

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Section: Baselinesmentioning

confidence: 99%

Section: Skipping Refreshmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Nonblocking Memory Refresh

Nguyen

Lyu

Meng

et al. 2018

2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA)

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“…Hence, it is infeasible during startup of a system to determine an exact list of weak cells that considers all parameters, such as temperature, retention time and DPD. A more recent idea, AVATAR [26], tries to overcome VRT issues by combining an online Error-Correcting Code (ECC) mechanism with row selective refresh. …”

Section: B Retention Aware Refreshmentioning

confidence: 99%

Efficient reliability management in SoCs - an approximate DRAM perspective

Jung

Mathew

Weis

et al. 2016

2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)

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In today's computing systems Dynamic Random Access Memories (DRAMs) have a large influence on performance and contribute significantly to the total power consumption. Thus, recent research activities bring the idea of approximate DRAM into focus to save power and improve performance by lowering the refresh rate or disabling refresh completely. Hence, fast and accurate models are required for a thoroughly exploration of approximate DRAM for error resilient applications. In this paper we present a holistic simulation environment for investigations on approximate DRAM and show the impact on error resilient applications.

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WinDRAM: Weak rows as in‐DRAM cache

Kumar

Sinha

Das

2022

Concurrency and Computation

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The primary factor responsible for increasing the refresh rate is the presence of weak rows in a DRAM. They have a shorter retention time and lose charge faster than regular rows. Recently, a technique known as in-DRAM cache was introduced in which some DRAM rows act as a separate module. The in-DRAM cache can be used for a variety of purposes in DRAM. We present WinDRAM, an in-DRAM cache comprised of all the DRAM's weak rows. The most recently accessed rows are copied into the in-DRAM cache so that when the row is accessed again, both rows (original and copy) can be activated at the same time. Such simultaneous activation reduces activation time and, as a result, DRAM access latency. Dual-row activation is the term for this concept. Because weak rows are part of the in-DRAM cache and are frequently accessed, WinDRAM does not perform a periodic refresh on them. Existing techniques based on in-DRAM cache do not design the in-DRAM cache using weak rows. WinDRAM proposes a novel idea by designing the in-DRAM cache using weak rows. Because the weak rows do not need to be refreshed, the refresh interval of the remaining rows can be increased, resulting in a refresh rate reduction of 80% to 90%. The speedup is 15% to 25% faster than standard DRAM and 12.77% faster than previous work for high memory-intensive workloads. Overall energy consumption is also reduced by 10% to 15%. K E Y W O R D SDRAM refresh, dual-row activation, in-DRAM cache, weak row INTRODUCTIONModern, high-performance computers require both on-chip and off-chip memory designs that are efficient. As the number of cores in modern multi-core systems increases, the need for bigger and more efficient main memory becomes crucial. With shrinking technological sizes, it becomes simpler to construct greater main memory as memory density increases. 1 However, it becomes increasingly difficult to reduce the energy consumption and access latency of such large memory. 1 Due to its improved density and capacity as well as its low production costs, DRAM has become the primary component of most contemporary main memories. 2,3 Typically, a DRAM bank is partitioned into many subarrays, as described in Section 2.Each subarray stores several DRAM cells in a 2D fashion (having rows and columns). Each DRAM cell is responsible for storing a single bit of data.The capacitor included within the cell stores the bit as a charge. For instance, a completely charged capacitor indicates that the cell contains bit 1.However, DRAM cells are leaky and lose their charge over a period of time (retention time). To keep the data contained within these cells, periodic refresh procedures must be done. Due to the recent increase in memory-intensive applications, the DRAM is being increased to meet their requirements. Consequently, the energy required to retain the data in the DRAM cells via periodic refresh increases essentially with the size of the main memory. 1 Refresh activities in a DRAM are accountable for up to fifty percent of the DRAM's power consumption. 4,5 In addition, these opera...

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AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems

Cited by 182 publications

References 27 publications

Nonblocking Memory Refresh

Nonblocking Memory Refresh

Efficient reliability management in SoCs - an approximate DRAM perspective

WinDRAM: Weak rows as in‐DRAM cache

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