Availability analysis for satellite data processing systems based on SRAM FPGAs

Siegle, Felix; Vladimirova, Tanya; Ilstad, Jørgen; Emam, O.

doi:10.1109/taes.2016.140914

Cited by 33 publications

(15 citation statements)

References 16 publications

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“…Fine-grained, non-invasive, and scalable fault detection in FPGA fabric is challenging, and subject of ongoing research [9], [10], and often is simply ignored [11]. Most FPGA-based FT-concepts rely on error scrubbing, which has scalability limitations for complex logic [9], [12], unless special-purpose offline testing is utilized [13]. In the future, memory-based reconfigurable logic devices (MRLDs) [14] may allow programmed logic to be protected like conventional memory, and thus would drastically simplify fault detection.…”

Section: Related Workmentioning

confidence: 99%

Dynamic Fault Tolerance Through Resource Pooling

Fuchs

Murillo

Plaat

et al. 2018

2018 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

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Miniaturized satellites are currently not considered suitable for critical, high-priority, and complex multi-phased missions, due to their low reliability. As hardware-side fault tolerance (FT) solutions designed for larger spacecraft can not be adopted aboard very small satellites due to budget, energy, and size constraints, we developed a hybrid FT-approach based upon only COTS components, commodity processor cores, library IP, and standard software. This approach facilitates fault detection, isolation, and recovery in software, and utilizes fault-coverage techniques across the embedded stack within a multiprocessor system-on-chip (MPSoC). This allows our FPGA-based proofof-concept implementation to deliver strong fault-coverage even for missions with a long duration, but also to adapt to varying performance requirements during the mission. The operator of a spacecraft utilizing this approach can define performance profiles, which allow an on-board computer (OBC) to trade between processing capacity, fault coverage, and energy consumption using simple heuristics. The software-side FT approach developed also offers advantages if deployed aboard larger spacecraft through spare resource pooling, enabling an OBC to more efficiently handle permanent faults. This FT approach in part mimics a critical biological system's ability to tolerate faults, adapt to permanent failure, and enables graceful aging of an MPSoC.

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Section: Related Workmentioning

confidence: 99%

Dynamic Fault Tolerance Through Resource Pooling

Fuchs

Murillo

Plaat

et al. 2018

2018 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

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“…But differently from the application on terrestrial systems, cosmic radiation may cause the failure of the on-board digital electronic systems [15], [16], so the reliability of the RS encoder and decoder becomes an important problem, especially for the decoder whose complexity is much higher than the encoder. On the other hand, SRAM based FPGAs (SRAM-FPGAs) are a popular option for on-board digital processing due to their rich logic resources and good reconfigurability [17], [18]. However, SRAM-FPGAs are more sensitive to cosmic radiation, and Single Event Upsets (SEUs) are the most frequent events [18], [19].…”

Section: Introductionmentioning

confidence: 99%

“…On the other hand, SRAM based FPGAs (SRAM-FPGAs) are a popular option for on-board digital processing due to their rich logic resources and good reconfigurability [17], [18]. However, SRAM-FPGAs are more sensitive to cosmic radiation, and Single Event Upsets (SEUs) are the most frequent events [18], [19]. SRAM-FPGAs can suffer two types of SEUs: errors on the configuration memory and errors on the user memory.…”

Section: Introductionmentioning

confidence: 99%

Design of FPGA-Implemented Reed–Solomon Erasure Code (RS-EC) Decoders With Fault Detection and Location on User Memory

Gao

Zhang

Cheng

et al. 2021

IEEE Trans. VLSI Syst.

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Reed-Solomon erasure codes (RS-EC) are widely used in packet communication and storage systems to recover erasures. When the RS-EC decoder is implemented on a FieldProgrammable Gate Array (FPGA) in a space platform, it will suffer Single Event Upsets (SEUs) that can cause failures. In this paper, the reliability of an RS-EC decoder implemented on an FPGA when there are errors in the user memory is firstly studied. Then a fault detection and localization scheme is proposed based on partial re-encoding for the faults in user memory of the RS decoder. Furthermore, check bits are added in the generator matrix to improve the fault location performance. Theoretical analysis shows that the scheme could detect most faults with small missing and false detection probability. Experimental results on a case study show that more than 90% faults on user memory could be tolerated by the decoder, and the all other faults can be detected by the fault detection scheme when the number of erasures is less than the correction capability of the code. Although false alarms exist (with probability smaller than 4%), they can be used to avoid faults accumulation. Finally, the fault location scheme could accurately locate all the faults. The theoretical estimates are very close to the experiment results, which verifies the correctness of the analysis done.

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“…Nevertheless, their application on-board satellites is highly complex mainly because they require significant memory and computational resources. Taking into account the increased use of field-programmable gate array (FPGA) technologies for space applications [10]- [12], the predictive coding techniques represents the best way to achieve a good compromise between performance (compression ratio) and complexity. Generally, predictive methods are preferred for lossless compression on satellites.…”

Section: Introductionmentioning

confidence: 99%

Implementation of CCSDS Standards for Lossless Multispectral and Hyperspectral Satellite Image Compression

Santos

Gómez

Sarmiento

2020

IEEE Trans. Aerosp. Electron. Syst.

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This paper presents the modeling, design, and implementation of two intellectual property (IP) cores that are compliant with the consultative committee for space data systems (CCSDS) 121.0-B-2 and CCSDS 123.0-B-1 lossless satellite image compression standards. The CCSDS 121.0-B-2 describes a lossless universal compressor based on a Rice adaptive encoding. The CCSDS 123.0-B-1 standard describes a lossless algorithm specifically designed for efficient on-board compression of hyperspectral and multispectral images, and it is based on a prediction and entropy-based encoding structure. Two options are offered for the latter: the sample-adaptive and the block-adaptive encoder, which corresponds to the CCSDS 121.0-B-2 algorithm. These IP cores have been designed as independent compressors, but they can be easily combined in a plug-and-play fashion to be used together thanks to a dedicated interface. Additionally, standard interfaces are provided for configuration and external memory access. The design process encompasses the consideration of several different hardware architectures in order to maximize throughput and optimize the requirements of on-board resources at the same time. Both IPs are compliant with the high degree of configurability considered in the standard. The obtained VHDL code is completely technology independent, so it can be used to target any field-programmable gate array (FPGA) or ASIC of interest in the space environment, aiming to perform efficiently compression in satellites despite the inherent

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Availability analysis for satellite data processing systems based on SRAM FPGAs

Cited by 33 publications

References 16 publications

Dynamic Fault Tolerance Through Resource Pooling

Dynamic Fault Tolerance Through Resource Pooling

Design of FPGA-Implemented Reed–Solomon Erasure Code (RS-EC) Decoders With Fault Detection and Location on User Memory

Implementation of CCSDS Standards for Lossless Multispectral and Hyperspectral Satellite Image Compression

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