AutoSVA: Democratizing Formal Verification of RTL Module Interactions

Orenes-Vera, Marcelo; Manocha, Aninda; Wentzlaff, David; Martonosi, Margaret

doi:10.1109/dac18074.2021.9586118

Cited by 5 publications

(3 citation statements)

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“…Meanwhile, studies in [20], [21] focus on leveraging LLMs to enhance BMC for identifying software vulnerabilities and deriving counterexamples. In [10], the authors trained GPT-4 to generate correct SystemVerilog Assertions (SVA) through iterative prompt refinement with rules. However, it remains unclear how these models derive answers and whether they rely on simple heuristics rather than a generated chain-ofthought [18].…”

Section: A Related Workmentioning

confidence: 99%

“…In the past several months, both academic and industry sectors have increasingly focused on applying LLMs in the realm of formal verification. Two major areas of this application are using prompt engineering and LLMs for hardware assertion [8]- [10] and software system Bounded Model Checking (BMC) [8], [9]. To our knowledge, no published work yet explores the use of LLMs in verifying communicationrelated protocols and specifications, especially for the large and complex protocols of 3GPP releases.…”

Section: Introductionmentioning

confidence: 99%

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Toward Auto-Modeling of Formal Verification for NextG Protocols: A Multimodal Cross- and Self-Attention Large Language Model Approach

Yang,

Wang

2024

IEEE Access

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This paper introduces Auto-modeling of Formal Verification with Real-world Prompting for 5G and NextG protocols (AVRE), a novel system designed for the formal verification of Next Generation (NextG) communication protocols, addressing the increasing complexity and scalability challenges in network protocol design and verification. Utilizing Large Language Models (LLMs), AVRE transforms protocol descriptions into dependency graphs and formal models, efficiently resolving ambiguities and capturing design intent. The system integrates a transformer model with LLMs to autonomously establish quantifiable dependency relationships through cross-and self-attention mechanisms. Enhanced by iterative feedback from the HyFuzz experimental platform, AVRE significantly advances the accuracy and relevance of formal verification in complex communication protocols, offering a groundbreaking approach to validating sophisticated communication systems. We compare CAL's performance with state-of-the-art LLM-based models and traditional time sequence models, demonstrating its superiority in accuracy and robustness, achieving an accuracy of 95.94% and an AUC of 0.98. This NLP-based approach enables, for the first time, the creation of exploits directly from design documents, making remarkable progress in scalable system verification and validation.

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Section: A Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Toward Auto-Modeling of Formal Verification for NextG Protocols: A Multimodal Cross- and Self-Attention Large Language Model Approach

Yang,

Wang

2024

IEEE Access

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“…The verification was conducted using industry-standard Sys-temVerilog Assertions (SVA) [25] and JasperGold [12] and assisting tools [42]. We followed a verification-first approach to save latestage debugging time and increase the confidence in creating a verifiably correct design.…”

Section: Formal Verification Of Maplementioning

confidence: 99%

Tiny but mighty

Orenes-Vera

Manocha

Balkind

et al. 2022

Proceedings of the 49th Annual International Symposium on Computer Architecture

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Modern computing systems employ significant heterogeneity and specialization to meet performance targets at manageable power. However, memory latency bottlenecks remain problematic, particularly for sparse neural network and graph analytic applications where indirect memory accesses (IMAs) challenge the memory hierarchy.Decades of prior art have proposed hardware and software mechanisms to mitigate IMA latency, but they fail to analyze real-chip considerations, especially when used in SoCs and manycores. In this paper, we revisit many of these techniques while taking into account manycore integration and verification.We present the first system implementation of latency tolerance hardware that provides significant speedups without requiring any memory hierarchy or processor tile modifications. This is achieved through a Memory Access Parallel-Load Engine (MAPLE), integrated through the Network-on-Chip (NoC) in a scalable manner. Our hardware-software co-design allows programs to perform longlatency memory accesses asynchronously from the core, avoiding pipeline stalls, and enabling greater memory parallelism (MLP).In April 2021 we taped out a manycore chip that includes tens of MAPLE instances for efficient data supply. MAPLE demonstrates a full RTL implementation of out-of-core latency-mitigation hardware, with virtual memory support and automated compilation targetting it. This paper evaluates MAPLE integrated with a dualcore FPGA prototype running applications with full SMP Linux, and demonstrates geomean speedups of 2.35× and 2.27× over softwarebased prefetching and decoupling, respectively. Compared to stateof-the-art hardware, it provides geomean speedups of 1.82× and 1.72× over prefetching and decoupling techniques. CCS CONCEPTS• Computer systems organization → Multicore architectures; Reconfigurable computing; Heterogeneous (hybrid) systems.

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