Automotive Functional Safety Assurance by POST with Sequential Observation

Wang, Senling; Higami, Yoshinobu; Takahashi, Hiroshi; Iwata, Hiroyuki; Matsushima, Jun

doi:10.1109/mdat.2018.2799801

Cited by 7 publications

(4 citation statements)

References 9 publications

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“…Finally, we show the experimental results on benchmark circuits to validate that the proposed methods can further reduce the number of scan-in patterns for achieving 90% stuck-at fault coverage compared to the SEQ-OB method presented in our previous paper [14], [15]. As a result, the proposed method is helpful to further shorten the TAT of POST.…”

Section: Discussionmentioning

confidence: 68%

“…In [14], we have proposed a method for selecting the FFs for SEQ OB which can assist the fault coverage improvement by analyzing the circuit-structure w/o using simulation. In [15] and [16] we have proposed a DFT technique named Fault-Detection-Strengthened (FDS) method for strengthening the fault detection capability of multicycle test to enhance the effect of SEQ-OB technique. Also, we have developed the underlying technologies including the FDS flip-flop (FF) design and an original in-house tool named FVP-TPI (Fault-effects-Vanishing Point-TPI) to compute the most effective insertion point of FDS FFs for SEQ OB based on the FF selection algorithm proposed in [14].…”

Section: ) the Low Power Consumptionmentioning

confidence: 99%

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FF-Control Point Insertion (FF-CPI) to Overcome the Degradation of Fault Detection under Multi-Cycle Test for POST

Al-Awadhi

Aono

Wang

et al. 2020

IEICE Trans. Inf. & Syst.

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Multi-cycle Test looks promising a way to reduce the test application time of POST (Power-on Self-Test) for achieving a targeted high fault coverage specified by ISO26262 for testing automotive devices. In this paper, we first analyze the mechanism of Stuck-at Fault Detection Degradation problem in multi-cycle test. Based on the result of our analysis we propose a novel solution named FF-Control Point Insertion technique (FF-CPI) to achieve the reduction of scan-in patterns by multi-cycle test. The FF-CPI technique modifies the captured values of scan Flip-Flops (FFs) during capture operation by directly reversing the value of partial FFs or loading random vectors. The FF-CPI technique enhances the number of detectable stuck-at faults under the capture patterns. The experimental results of ISCAS89 and ITC99 benchmarks validated the effectiveness of FF-CPI technique in scan-in pattern reduction for POST.

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Section: Discussionmentioning

confidence: 68%

Section: ) the Low Power Consumptionmentioning

confidence: 99%

FF-Control Point Insertion (FF-CPI) to Overcome the Degradation of Fault Detection under Multi-Cycle Test for POST

Al-Awadhi

Aono

Wang

et al. 2020

IEICE Trans. Inf. & Syst.

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“…This paper proposes a novel scheme using weight-aware scan grouping and scheduling (WGS) to enhance fault coverage and reduce switching activity with limited test time and hardware overhead. Since the test time required for each automotive product to perform the online or offline test is limited [44], our method freezes the test time in advance and focuses on significantly improving both the target factors. Most of the previous methods can handle the high toggling level of random patterns; however, they negatively affect fault coverage.…”

Section: Introductionmentioning

confidence: 99%

A Low-Power BIST Scheme Using Weight-Aware Scan Grouping and Scheduling for Automotive ICs

Lee

Park

et al. 2021

IEEE Access

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Scan-based logic built-in self-test (LBIST) is widely used for supporting the in-system test in automotive systems. Although this technology has the advantage of low-cost testing, it suffers from low fault coverage and high switching activity during the test. This can lead to many undetected defects, excessive heat dissipation, and IR drop, inducing catastrophic risks to functional safety. Therefore, improving these two key factors is crucial to alleviate reliability problems in the automotive domain. Most previous works have focused on controlling the enormous toggling level of random patterns; however, one of the main disadvantages of these approaches is low fault coverage. Unfortunately, additional hardware costs associated with memory elements or test points are required for detecting the remaining faults. We propose a novel LBIST scheme based on weight-aware scan grouping and scheduling (WGS) to overcome these difficulties. Since the required test time of each automotive product is limited, the proposed scheme freezes the test time and focuses on improving both aforementioned factors significantly. Our approach divides scan cells into two categories: the coverage-efficient scan group and power-efficient scan group, and then it conducts weightbased scan cell reordering. Biased random patterns are fed to enhance fault coverage for the first category. For the second category, scheduling and disabling are performed to reduce switching activity. Finally, physical-aware reordering based on an inverter is performed to reduce routing overhead. Experimental results demonstrate the feasibility of the WGS methodology on the ITC'99 and OpenRISC benchmark circuits.INDEX TERMS Design for testability, low-power testing, scan-based logic BIST, scan cell ordering, scan chain scheduling.

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“…POST is having limited test application time in automotive systems [8]. Getting required LF coverage (>90%) within less test application time is primary requirement [9]. the pass/fail comparison of the unit [10], [11].…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of DFT Technique to Verify LBIST at RTL Level

Vannal¹,

Siddamal²

2020

Adv. sci. technol. eng. syst. j.

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According to IEC 61805 and ISO 26262 standards requirement inclusion of LBIST (Logic Built in Self-Test) became mandatory to achieve safety critical application such as automotive field. In such systems, once device is switched ON LBIST (Logic Built in Self-Test) is activated and testing of digital logic is performed. After safety subsystem says that the LBIST passed, the SoC (System on Chip) moves into the functional mode otherwise, the SoC moves into a safe state. In this entire start-up sequence the LBIST interacts extensively with the safety sub-system of the SoC. Startup sequence remains un-verified at RTL (Register-Transfer Level) leading to painful ECOs (Engineering Change Orders) and post Silicon issues in some cases. LBIST verification can only run if scan chains are present in design which is not the case at RTL. The paper describes design of a Design-for-Testability (DFT) technique to enable LBIST based system verification with different test approaches at RTL which eliminates the possibility of ECOs by catching most of the issues at RTL level. Simulation results are demonstrating the feasibility of the approach with emphasizing the benefits obtained on significant computational modules.

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Automotive Functional Safety Assurance by POST with Sequential Observation

Cited by 7 publications

References 9 publications

FF-Control Point Insertion (FF-CPI) to Overcome the Degradation of Fault Detection under Multi-Cycle Test for POST

FF-Control Point Insertion (FF-CPI) to Overcome the Degradation of Fault Detection under Multi-Cycle Test for POST

A Low-Power BIST Scheme Using Weight-Aware Scan Grouping and Scheduling for Automotive ICs

Design and Implementation of DFT Technique to Verify LBIST at RTL Level

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