Automotive 130 nm smart-power-technology including embedded flash functionality

Rudolf, Ralf; Wagner, C.; O'Riain, Lincoln; Gebhardt, Karl-Heinz; Kuhn-Heinrich, Barbara; Ehrenwall, Birgit von; Ehrenwall, Andreas von; Strasser, Marc; Stecher, M.; Glaser, Ulrich; Aresu, Stefano; Kuepper, P.; Mayerhofer, A.

doi:10.1109/ispsd.2011.5890780

Cited by 34 publications

(13 citation statements)

References 10 publications

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“…The devices used are p-channel Lateral DMOS transistors (PLD-MOS), processed in a 130 nm smart power technology with 5 nm gate oxide thickness [10]. Shallow in the device drift region (see Fig.…”

Section: Methodsmentioning

confidence: 99%

HCS degradation of 5nm oxide high-voltage PLDMOS

Olk

Aresu

Rudolf

et al. 2014

Microelectronics Reliability

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Section: Methodsmentioning

confidence: 99%

HCS degradation of 5nm oxide high-voltage PLDMOS

Olk

Aresu

Rudolf

et al. 2014

Microelectronics Reliability

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“…The devices were manufactured using a 130 nm SmartPower-Technology process node [16]. There were only a few wafers affected by the problem.…”

Section: Electrical Testmentioning

confidence: 99%

Scanning spreading resistance microscopy for failure analysis of nLDMOS devices with decreased breakdown voltage

Doering

Rudolf

Pinkert

et al. 2014

Microelectronics Reliability

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“…Deep Trench (DT) ensures the lateral isolation of the epi-wells. Shallow Trench Isolation (STI) is used instead of field oxide in the device drift region [2].…”

Section: Samples and Measurementsmentioning

confidence: 99%

Hot-carrier and recovery effect on p-channel lateral DMOS

Aresu

Vollertsen

Rudolf

et al. 2011

2011 IEEE International Integrated Reliability Workshop Final Report

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Hot-carrier, inducing source-drain current (I DS ) increase in highvoltage p-channel lateral DMOS (LDMOS) transistors, is investigated. At low gate voltage (V GS ) and high drain voltage (V DS ), electrons are injected into the gate oxide, creating negative fixed oxide charges and interface-states above the accumulation region and the channel towards the source side (Figure 1). The source drain current (I DS ) increase leads to threshold voltage shift (V TH 0V) and for higher stress conditions a drain-source leakage can be observed. The effect has been analyzed combining experimental data and TCAD simulations. For the first time recovery effect after hot carrier stress even at low temperature is reported.

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Automotive 130 nm smart-power-technology including embedded flash functionality

Cited by 34 publications

References 10 publications

HCS degradation of 5nm oxide high-voltage PLDMOS

HCS degradation of 5nm oxide high-voltage PLDMOS

Scanning spreading resistance microscopy for failure analysis of nLDMOS devices with decreased breakdown voltage

Hot-carrier and recovery effect on p-channel lateral DMOS

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