Automating production of run-time reconfigurable designs

Shirazi, N.; Luk, Wayne; Cheung, Peter Y. K.

doi:10.1109/fpga.1998.707892

Cited by 51 publications

(20 citation statements)

References 6 publications

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“…For designs with clock gating or with partial bit-streams, identical regions in successive configurations are extracted to minimise area or to minimise the reconfiguration overhead. An efficient algorithm based on weighted bipartite graphs [16] has been proposed to automate this step.…”

Section: Multiplexer-based Reconfigurationmentioning

confidence: 99%

Reconfigurable design with clock gating

Osborne¹,

Luk²,

Coutinho³

et al. 2008

2008 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation

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This paper describes an approach for developing energyoptimized run-time reconfigurable designs which benefit from clock gating. The approach is applied to two techniques: multiplexer-based reconfiguration, and reconfigurable wordlength optimization. The conditions under which this approach would be preferable to bit-stream reconfiguration are derived. Various case studies, such as ray tracing, guitar string simulation and matrix-vector multiplication, are used to illustrate this approach.

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Section: Multiplexer-based Reconfigurationmentioning

confidence: 99%

Reconfigurable design with clock gating

Osborne¹,

Luk²,

Coutinho³

et al. 2008

2008 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation

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“…The absence of CAD tools that support the design flow of reconfigurable circuits and the lack of published application expertise are certainly some of the main difficulties that a designer of reconfigurable circuits must handle [Hutchings95). On the other hand several research groups have developed applications that prove the possibility (and in some cases the economic efficiency) of dynamically reconfigurable applications [Eldredge96,Wirthlin95,Robinson98,Shirazi98,Sklyarov98).…”

Section: Introductionmentioning

confidence: 99%

Dynamically Reconfigurable Implementation of Control Circuits

Lau

Sklyarov

2000

VLSI: Systems on a Chip

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Abstract:Control Circuits can be described using a top-down approach with the aid of Hierarchical Graph-Schemes (HGSs). The implementation of HGSs in a finegrain FPGA has been done using a Hierarchical Finite State Machine structure where each sub-algorithm implementation is independent from the others. Static and dynamically reconfigurable implementations using the XC6200 FPGA have been obtained by applying a number of commercial design tools together with tools developed by the authors.

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“…SPARCS [2] is an integrated partitioning and synthesis framework, which has a temporal partitioning tool to temporally divide and schedule the tasks on a reconfigurable system. Shirazi et al [3] proposed a methodology to take advantage of common operators in successive configurations. They attempted to reduce configuration time and thus, the application execution time.…”

Section: Introductionmentioning

confidence: 99%

A gravity-directed temporal partitioning approach

Mehdipour

Noori

Honda

et al. 2008

IEICE Electron. Express

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Reconfiguration latency has a significant impact on the system performance in reconfigurable systems. A temporal partitioning approach is introduced for partitioning data flow graphs for a reconfigurable system comprising a partial programmable fine-grained hardware. Residing eligibility inspired from the Universal gravitation law is introduced to depict the eligibility of a node to stay in succeeding configurations (partitions) and to prohibit it from being swapped in/out. Partitioning based on residing eligibility causes fewer nodes with different functionalities to be assigned to subsequent partitions. Thus, reconfiguration overhead time and also unused hardware space decreases due to common parts in consecutive configurations.

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Automating production of run-time reconfigurable designs

Cited by 51 publications

References 6 publications

Reconfigurable design with clock gating

Reconfigurable design with clock gating

Dynamically Reconfigurable Implementation of Control Circuits

A gravity-directed temporal partitioning approach

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