Automating Customisation of Floating-Point Designs

Gaffar, A.A.; Luk, Wayne; Cheung, Peter Y. K.; Shirazi, N.; Hwang, J.C.M.

doi:10.1007/3-540-46117-5_55

Cited by 21 publications

(12 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Authors in [11,12] presented works on building FP units of word width shorter than 64 bits, optimized for FPGAs. The authors of [1,17] propose customizable designs of floating-point units used in the development of automatic design tools. In [10], a memory organization for efficient access of rectangular data blocks is proposed.…”

Section: Comparisons To Related Workmentioning

confidence: 99%

64-bit floating-point FPGA matrix multiplication

Dou¹,

Vassiliadis

Kuzmanov

et al. 2005

Proceedings of the 2005 ACM/SIGDA 13th International Symposium on Field-Programmable Gate Arrays

163

117

View full text Add to dashboard Cite

We introduce a 64-bit ANSI/IEEE Std 754-1985 floating point design of a hardware matrix multiplier optimized for FPGA implementations. A general block matrix multiplication algorithm, applicable for an arbitrary matrix size is proposed. The algorithm potentially enables optimum performance by exploiting the data locality and reusability incurred by the general matrix multiplication scheme and considering the limitations of the I/O bandwidth and the local storage volume. We implement a scalable linear array of processing elements (PE) supporting the proposed algorithm in the Xilinx Virtex II Pro technology. Synthesis results confirm a superior performance-area ratio compared to related recent works. Assuming the same FPGA chip, the same amount of local memory, and the same I/O bandwidth, our design outperforms related proposals by at least 1.7X and up to 18X consuming the least reconfigurable resources. A total of 39 PEs can be integrated into the xc2vp125-7 FPGA, reaching performance of, e.g., 15.6 GFLOPS with 1600 KB local memory and 400 MB/s external memory bandwidth.

show abstract

Section: Comparisons To Related Workmentioning

confidence: 99%

64-bit floating-point FPGA matrix multiplication

Dou¹,

Vassiliadis

Kuzmanov

et al. 2005

Proceedings of the 2005 ACM/SIGDA 13th International Symposium on Field-Programmable Gate Arrays

163

117

View full text Add to dashboard Cite

show abstract

“…There exist also parameterized IP cores which offer particularly efficient implementations for a given architecture. Fully parameterizable floating point libraries [1,11] allow extensive explorations of different precisions and methods for automatic optimization of the operand sizes have been proposed [12,13]. Another option for FPGAs is to use logarithmic number systems which avoid the quadratic complexity of the multiplier but complicate the adder [18,23].…”

Section: Floating Point Numbers On Fpgasmentioning

confidence: 99%

Pipelined Mixed Precision Algorithms on FPGAs for Fast and Accurate PDE Solvers from Low Precision Components

Strzodka¹,

Göddeke

2006

2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines

View full text Add to dashboard Cite

FPGAs are becoming more and more attractive for high precision scientific computations. One of the main problems in efficient resource utilization is the quadratically growing resource usage of multipliers depending on the operand size. Many research efforts have been devoted to the optimization of individual arithmetic and linear algebra operations. In this paper we take a higher level approach and seek to reduce the intermediate computational precision on the algorithmic level by optimizing the accuracy towards the final result of an algorithm. In our case this is the accurate solution of partial differential equations (PDEs). Using the Poisson Problem as a typical PDE example we show that most intermediate operations can be computed with floats or even smaller formats and only very few operations (e.g. 1%) must be performed in double precision to obtain the same accuracy as a full double precision solver. Thus the FPGA can be configured with many parallel float rather than few resource hungry double operations. To achieve this, we adapt the general concept of mixed precision iterative refinement methods to FPGAs and develop a fully pipelined version of the Conjugate Gradient solver. We combine this solver with different iterative refinement schemes and precision combinations to obtain resource efficient mappings of the pipelined algorithm core onto the FPGA.

show abstract

“…The use of custom floating-point formats in FPGAs has been investigated in a long series of work [1,2,3,4,5]. In most of the cases, these formats are shown to be adequate for some applications that require significantly less area to implement than IEEE formats [6] and to run significantly faster than IEEE formats.…”

Section: Introductionmentioning

confidence: 99%

Design of FPGA based 32-bit Floating Point Arithmetic Unit and verification of its VHDL code using MATLAB

Grover¹,

Soni²

2014

IJIEEB

View full text Add to dashboard Cite

-Most of the algorithms implemented in FPGAs used to be fixed-point. Floating-point operations are useful for computations involving large dynamic range, but they require significantly more resources than integer operations. With the current trends in system requirements and available FPGAs, floating-point implementations are becoming more common and designers are increasingly taking advantage of FPGAs as a platform for floating-point implementations. The rapid advance in Field-Programmable Gate Array (FPGA) technology makes such devices increasingly attractive for implementing floating-point arithmetic. Compared to Application Specific Integrated Circuits, FPGAs offer reduced development time and costs. Moreover, their flexibility enables field upgrade and adaptation of hardware to run-time conditions. A 32 bit floating point arithmetic unit with IEEE 754 Standard has been designed using VHDL code and all operations of addition, subtraction, multiplication and division are tested on Xilinx. Thereafter, Simulink model in MAT lab has been created for verification of VHDL code of that Floating Point Arithmetic Unit in Modelsim.

show abstract

Automating Customisation of Floating-Point Designs

Cited by 21 publications

References 8 publications

64-bit floating-point FPGA matrix multiplication

64-bit floating-point FPGA matrix multiplication

Pipelined Mixed Precision Algorithms on FPGAs for Fast and Accurate PDE Solvers from Low Precision Components

Design of FPGA based 32-bit Floating Point Arithmetic Unit and verification of its VHDL code using MATLAB

Contact Info

Product

Resources

About