Automatic Verification of External Interrupt Behaviors for Microprocessor Design

Yang, Fu-Ching; Huang, Wenmei; Huang, Ing-Jer

doi:10.1109/dac.2007.375291

Cited by 1 publication

(1 citation statement)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In order to verify the functionality of the DUV, it is also necessary to tests the core while handling interrupts, instruction and data bus delays (e.g., due to contention in multi-master bus or cache misses) along with the Software (SW) exceptions and normal instructions. Such events cannot be triggered using only instructions; therefore, external devices are involved to stimulate those conditions [31]. For this reason, a hardware implementation of the perturbation module has been designed to provide interrupt requests and bus stalls during RTL simulations.…”

Section: Figure 2 Ri5cy Architecturementioning

confidence: 99%

An Open-Source Verification Framework for Open-Source Cores: A RISC-V Case Study

Schiavone

Sánchez

Ruospo

et al. 2018

2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)

View full text Add to dashboard Cite

The complexity and heterogeneity of digital devices used in embedded systems is increasing everyday and delivering a bug-free design is still a very complex task. The interest for open-source hardware in real products is demanding for tools and advanced methodologies for verification to provide high reliability to open and free IPs. In this work, an opensource evolutionary optimizer has been used to create functional test programs that improve the verification test set for an open-source microprocessor, enhancing in this way, the verification level of the device. The verification programs are generated to optimize code coverage metrics and are tested against a high-level model to find device incorrectnesses during the generation time. A perturbation mechanism has been included in the verification framework to cover parts of the device under verification not reachable with only software stimuli such as interrupts or memory stalls. The proposed methodology uncovered 10 bugs still present in the RTL description of the analyzed device and demonstrated the effectiveness of opensource verification tools for the next generation of open-source RISC-V microprocessors.

show abstract

Section: Figure 2 Ri5cy Architecturementioning

confidence: 99%