Automatic Thermal Network Extraction and Multiscale Electro-Thermal Simulation

Abstract

We present a new strategy to perform chip-level electro-thermal simulation. In our approach electrical behaviour of each circuit element is modeled by standard compact models with an added temperature node (1; 2). Mutual heating is accounted for by a 2-D or 3-D diffusion reaction PDE, which is coupled to the electrical network by enforcing instantaneous energy conservation. To cope with the multiscale nature of heat diffusion in VLSI circuit a suitable spatial discretization scheme is adopted which allows for efficient meshing of large domains with details at a much smaller scale. Preliminary numerical results on a realistic test case are included as a validation of the model and of the numerical method

Automated netlist generation for 3D electrothermal and electromagnetic field problems

“…Generating compact models from the calculated or measured response function is another popular approach and has been followed by Evans et al and Bernardoni et al [39,40]. For thermal problems, methods that derive an equivalent circuit directly from the mesh can also be found [41,42], but none of them accounts for the ET coupling. Karagol and Bikdash [43] presented an approximate representation obtained from a graph-partitioning algorithm of an FEM mesh resulting in a medium-sized ET circuit.…”

“…The above equation holds for any component of E. Furthermore, if the field E propagates in free space, we may assume that the operation ∇ 2 t is negligible in the neighbourhood of an observation point within the spherical wavefront. Hence, we may rewrite (41) in terms of simplified inward and outward travelling wave propagators as…”