Automatic test vector cultivation for sequential VLSI circuits using genetic algorithms

Saab, D.G.; Saab, Youssef; Abraham, Jacob A.

doi:10.1109/43.541447

Cited by 37 publications

(9 citation statements)

References 24 publications

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“…On the other hand, simulation based functional verification techniques [11,10,24] show the following problems:…”

Section: Introductionmentioning

confidence: 99%

“…The verification of a digital system at the various steps of its design life is an activity that can be performed adopting a simulation approach [11,10,24] or, a less popular, although extremely appealing for its promises of exhaustiveness, formal method [22,6,17,2,20]. Both strategies have strengths and weaknesses and the inherent complexity of the verification activity of non trivial systems leads to the need to budget time, human and hardware resources involved in the verification activity to be engaged up to the moment in which a reasonable confidence in system implementation correctness is reached.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

An error simulation based approach to measure error coverage of formal properties

Azzoni¹,

Fedeli

Fummi³

et al. 2002

Proceedings of the 12th ACM Great Lakes Symposium on VLSI - GLSVLSI '02

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Many approaches have been proposed for digital system verification, either based on simulation strategies or on formal verification techniques. Both of them show advantages and drawbacks and new mixed approaches have been presented in order to improve the verification process. Specifically, the adoption of formal methods still lacks a coverage metrics to let the verification engineer get a measure of which portion of the circuit is already covered by the written properties that far and which parts still need to be addressed. The present paper describes a new simulation based methodology aimed at measuring the error coverage achieved by temporal assertions proved by model checking. The approach has been applied to the description of a protocol converter block, and some preliminary results are presented in the paper.

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“…On the other hand, simulation based functional verification techniques [11,10,24] show the following problems:…”

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

An error simulation based approach to measure error coverage of formal properties

Azzoni¹,

Fedeli

Fummi³

et al. 2002

Proceedings of the 12th ACM Great Lakes Symposium on VLSI - GLSVLSI '02

View full text Add to dashboard Cite

show abstract

“…The adopted crossover operator exploits problem specific knowledge, thus making hard to identify the real contribution of GA's independently from the adopted heuristics. The performance of the CRlS test generator [Z] has been improved in [4] by using a fault simulation procedure to evaluate the generated sequences. The fault coverage increases as well as the execution time.…”

Section: Ga's For Gate-level Testingmentioning

confidence: 99%

Genetic algorithms: the philosopher's stone or an effective solution for high-level TPG?

Fin

Fummi

Eighth IEEE International High-Level Design Validation and Test Workshop

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The paper esamines the potentialities of genetic algorithms (GA ' a) with respect to the development of high-level TPG's. It summarizes atfirst the most relevant test pattern genemtion techniques based on genetic algorithms (GA ' s ) . This analysis distinguishes the considered techniques with respect to the abstraction level of the design under test. I n particular, the effectiveness of gate-level GA-based TPG's is compared with the effectiveness of high-level CA-based TPG's. Differences are deeply investigated. They mainly concern the way genetic operators ezploit specific simulation information to heuristically guide the genetic evolution. Moreover, a functional testing fmmework is described and used to actually measure on high-level descriptions the effectiveness of sophisticated CA-based TPC's in comparison to mndom approaches. Results are reported on a variety of benchmnrks. '1. INTRODUCTIONGA's [I] have been shown to he effective when solving search problems. In the area of test generation of VLSI designs, GA's have been adopted as TPG engines at gate level and high level (e.g., RTL and behavioral). Section 1.1 and 1.2 show their respective characteristics, which are summarized and compared in Section 1.3. Section 2 describes the proposed testing framework, which allows to compare the reviewed GA techniques.Experimental results, presented in Sect.ion 3, show evidences i n the use of GA's for high-level TPG. GA's for Gate-level TestingGA's have been used at first as a framework for simulationbased test generation in 121 and [3]. Both techniques target gatelevel descriptions. The former adopt a logic simulator to evaluate the generated test sequences, thus the generated test sets have often a lower fault coverage than that generated by a deterministic test generat.or. The later targets only combinational circuits. The adopted crossover operator exploits problem specific knowledge, thus making hard to identify the real contribution of GA's independently from the adopted heuristics. The performance of the CRlS test generator [Z] has been improved in [4] by using a fault simulation procedure to evaluate the generated sequences. The fault coverage increases as well as the execution time. The adopted fitness function is defined as: vi,j I (Np -Np) I< a (1) where t,he symbol NF and NF represent the number of changes of suh-circuits i and j due to the application of a sequence of 'Research activity partially supported by the IST-2001-34607 SYXIBAD European Project. length R and a is an appropriate small integer value. Other effective solutions targeting synchronous circuits have been proposed in [5] and [6]. The latter represents an extension of the former work, where up to 64 faults have been targeted simultaneously. GA's are used to propagate the induced faulty values to the design primary outputs. These techniques are suitable only for designs with a reset state. The adopted fitness function is: p= 1 ,"=I where ny.te and nF.r are respectively the number of gates and flip-flops, 4 is the k-th vector of sequen...

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“…The test generation problem belongs to the latter. In 1992, the use of genetic algorithms for test generation was first reported [2,3], in which the fitness of an individual in the GA is based on balanced circuit activity. An approach [4,5] was only for combinational circuits.…”

Section: Introductionmentioning

confidence: 99%

Genetic algorithm based test generation for sequential circuits

Shen¹

Proceedings Eighth Asian Test Symposium (ATS'99)

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This paper deals with simulation and genetic algorithm (GA) based test generation for sequential circuits. We proposed a new sequential depth measure called sequential element reachability, which may be used as one of parameters of GA. For fitness functions, we proposed a new dynamic testability measure, which can be evaluated in parallel for multiple individuals. The test generation is divided to three sub-problems: initialization, test vector generation for a group of faults and test sequence generation for a target fault. Using ISCAS89 benchmarks, the experiment results of GA were given.

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Automatic test vector cultivation for sequential VLSI circuits using genetic algorithms

Cited by 37 publications

References 24 publications

An error simulation based approach to measure error coverage of formal properties

An error simulation based approach to measure error coverage of formal properties

Genetic algorithms: the philosopher's stone or an effective solution for high-level TPG?

Genetic algorithm based test generation for sequential circuits

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