Automatic technique of distortion compensation in resistor ladder for high-speed and low-power ADC

Abstract

A Resistor ladder is an important circuit block for parallel architecture analog-to-digital converters (ADCs). The output of ADC suffers from distortion due to kickback noise from comparators when the bias current of the resistor ladder is reduced to reduce its power dissipation. A technique of distortion compensation that cancels kickback noise by injecting compensation current to the resistor ladder has been known to overcome this problem. This technique, however, did not consider that kickback noise depends on the sampling frequency and variability of resistors. Therefore, we propose an automatic circuit for distortion compensation that detects the amount of kickback noise and properly adjusts the compensation current. The simulation results demonstrated that distortion could be reduced with the proposed technique even when the changes in sampling frequency and deviations in the resistor occurred.