Automatic scan insertion and test generation for asynchronous circuits

Beest, Frank te; Peeters, A.; Verra, M.; Berkel, Kees van; Kerkhoff, Hans G.

doi:10.1109/test.2002.1041834

Cited by 19 publications

(11 citation statements)

References 14 publications

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“…Additionally, a synchronous clock tree imposes timing and power considerations which should have been avoided with the asynchronous design methodology. Other approaches propose the extension of the handshake control logic and registers to support the shift operations for scanning patterns in and out [7], [11]- [13]. Besides the synchronization, a further issue of the pattern shifting results from the sequential elements used.…”

Section: B Scan-testmentioning

confidence: 99%

See 1 more Smart Citation

A survey about testing asynchronous circuits

Zeidler

Krstić

2015

2015 European Conference on Circuit Theory and Design (ECCTD)

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Even though the asynchronous design methodology is considered to be a promising solution to upcoming challenges of designing complex integrated circuits (ICs), it is not widely accepted by the industry. Besides the lack of mature design tools, a further key inhibitor of using this design style is the widespread assumption that asynchronous circuits are difficult to test due to problems with system timing during test, nondeterminism, and difficulties with applying standard test approaches such as scan. However, there is a huge variety of approaches to handle these testing issues. This paper summarizes the different available test methodologies for asynchronous and globallyasynchronous locally-synchronous (GALS) designs and addresses their strengths and weaknesses. Moreover, it gives an overview of a methodology for testing based on the use of specific test processor, developed by IHP.

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Section: B Scan-testmentioning

confidence: 99%

“…1b. In normal mode these elements are transparent in order to maintain the original behavior of the circuit [13]. In scan mode, the test patterns are shifted in and out.…”

Section: B Scan-testmentioning

confidence: 99%

A survey about testing asynchronous circuits

Zeidler

Krstić

2015

2015 European Conference on Circuit Theory and Design (ECCTD)

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“…The technique is simple, easy to implement, and gives very good results in practice even if the model used does not fully match the real faults. In the meantime some of the asynchronous designs have become scan-testable [12]. Synchronous design is, by default, scan-friendly.…”

Section: Test Strategiesmentioning

confidence: 99%

“…Testing is also still in its infancy for these types of designs, although recently much effort has been invested to find suitable and easy-to-use testing strategies for asynchronous designs [12].…”

Section: Introductionmentioning

confidence: 99%

Scan Test Strategy for Asynchronous-Synchronous Interfaces

Petre¹,

Kerkhoff²

2004

J Electron Test

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In the coming years, the well-known synchronous design style will not be able to keep pace with the increase speed and capabilities of integration of advanced processes. New design paradigms, like core reuse of the already designed synchronous modules and asynchronous designs, are considered in order to cope with the ever increasing complexity. The future SoCs will contain multiple synchronous and asynchronous cores. Asynchronous design will become more and more common among digital designers, while synchronous-asynchronous interactions will emerge as a key issue in the future SoC designs. This paper will present test strategies for 2-phase asynchronous-synchronous interfaces and vice versa. It will be shown how test vectors can be automatically generated using commercially available ATPG tools. The generated ATPG vectors will be able to test all stuck-at-faults within the asynchronous-synchronous interfaces.

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“…One popular test solution is to integrate scan paths into the asynchronous design (cf. [3], [4], [5]), since this technique is established for synchronous systems and accepted by the industry. Unfortunately, introducing scan paths is a large overhead due to the integration of a clock tree that should be avoided within asynchronous designs.…”

Section: Introductionmentioning

confidence: 99%

Ultra low cost asynchronous handshake checker

Zeidler

Ehrig

Krstić

et al. 2009

2009 15th IEEE International on-Line Testing Symposium

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This paper presents a new on-line checking scheme for asynchronous handshake protocols. The proposed scheme requires very small chip area while maintaining high coverage for all considered faults which are briefly exposed. In addition to simple pass-fail information the checker provides off-line diagnosis capabilities in order to further analyze the cause of a fault and the time of its occurrence. In order to verify its functionality the checker was proven by performing analogue simulations. In addition the area overhead and the power consumption was determined and compared with existing implementations.

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Automatic scan insertion and test generation for asynchronous circuits

Cited by 19 publications

References 14 publications

A survey about testing asynchronous circuits

A survey about testing asynchronous circuits

Scan Test Strategy for Asynchronous-Synchronous Interfaces

Ultra low cost asynchronous handshake checker

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