Automatic Parallelization of Simulink Models for Multi-core Architectures

Tuncali, Cumhur Erkan; Fainekos, Georgios; Lee, Yann-Hang

doi:10.1109/hpcc-css-icess.2015.232

Cited by 10 publications

(9 citation statements)

References 13 publications

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“…One popular approach is to alter the Simulink block diagram to reflect the mapping of tasks to cores before generating serial code, and then making relatively minor changes to facilitate multithreading. References [8], [15], and [17] achieved varying levels of automation using such approaches, while targeting homogeneous architectures.…”

Section: Previous and Related Workmentioning

confidence: 99%

Code Generation from Simulink Models with Task and Data Parallelism

Xu¹,

Edahiro

Kondo³

2021

IJCT

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In this paper, we propose a method to automatically generate parallelized code from Simulink models, while exploiting both task and data parallelism. Building on previous research, we propose a model-based parallelizer (MBP) that exploits task parallelism and assigns tasks to CPU cores using a hierarchical clustering method. We also propose amethod in which data-parallel SYCL code is generated from Simulink models; computations with data parallelism are expressed in the form of S-Function Builder blocks and are executed in a heterogeneous computing environment. Most parts of the procedure can be automated with scripts, and the two methods can be applied together. In the evaluation, the data-parallel programs generated using our proposed method achieved a maximum speedup of approximately 547 times, compared to sequential programs, without observable differences in the computed results. In addition, the programs generated while exploiting both task and data parallelism were confirmed to have achieved better performance than those exploiting either one of the two.

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Section: Previous and Related Workmentioning

confidence: 99%

Code Generation from Simulink Models with Task and Data Parallelism

Xu¹,

Edahiro

Kondo³

2021

IJCT

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“…Currently, a large amount of research is being done on implementing control models in MBD with Simulink. Commonly, Simulink blocks are partitioned and parallelized to processing elements of the target platform using heuristic algorithms [6] or mathematical methods [7,8,9], and execution codes are generated based the sequential codes generated by Simulink Embedded Coder [10]. In previous studies, we used integer linear programming (ILP)based approaches to parallelize Simulink models on homogeneous multicore processors [11] and single-ISA heterogeneous multicore processors [12].…”

Section: Related Workmentioning

confidence: 99%

Model-Based Parallelization for Simulink Models on Multicore CPUs and GPUs

Zhang

Edahiro

2020

IJCT

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In this paper we propose a model-based approach to parallelize Simulink models of image processing algorithms on homogeneous multicore CPUs and NVIDIA GPUs at the block level and generate CUDA C codes for parallel execution on the target hardware. In the proposed approach, the Simulink models are converted to directed acyclic graphs (DAGs) based on their block diagrams, wherein the nodes represent tasks of grouped blocks or subsystems in the model and the edges represent the communication behaviors between blocks. Next, a path analysis is conducted on the DAGs to extract all execution paths and calculate their respective lengths, which comprises the execution times of tasks and the communication times of edges on the path. Then, an integer linear programming (ILP) formulation is used to minimize the length of the critical path of the DAG, which represents the execution time of the Simulink model. The ILP formulation also balances workloads on each CPU core for optimized hardware utilization. We parallelized image processing models on a platform of two homogeneous CPU cores and two GPUs with our approach and observed a speedup performance between 8.78x and 15.71x.

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“…In addition, it is difficult to extract block allocation results for user feedback and model evaluation in code-level parallelization. Meanwhile, for model-level parallelization [8,9,11], the extraction of block-level parallelism from models is common. These blocks are partitioned to the cores on the processor.…”

Section: Related Workmentioning

confidence: 99%

“…The communication time between different cores must also be taken into account to solve this problem. In this case, linear programming (LP) introduces an appropriate solution to solve such problems [9,10,11]. We can describe Simulink models and target processors in an LP formulation and give it suitable constraints, followed by using LP solvers to solve the formulation for the optimal solution.…”

Section: Related Workmentioning

confidence: 99%

“…It solves the model-level parallelization problems for processors with ARM big.LITTLE architecture and generates static core assignment solution of the Simulink models. Static core assignment, such as ILP [11] and graph partition [12,13], is more suitable for embedded control applications, as compared to dynamic task allocation. Static core assignment does not need to run a task scheduler to determine the execution of blocks, which leads to a much smaller overhead in the execution of the application.…”

Section: Related Workmentioning

confidence: 99%

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Model-Based Parallelizer for Embedded Control Systems on Single-ISA Heterogeneous Multicore

Zhang

2019

IJCT

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This paper presents a model-based parallelization approach to parallelize embedded systems on single-ISA heterogeneous multicore processors, especially processors with the ARM big.LITTLE architecture, wherein the core assignment of the Simulink blocks is determined based on the control design constraints and characteristics of the big.LITTLE architecture. The proposed approach uses a hierarchical clustering method on Simulink blocks to reduce the problem scale, and an integer linear programming (ILP) formulation to determine the core assignment solution, considering load balancing and minimization of inter-core communication across cores with different performances. Finally, we generate the parallel code of the model based on the core assignment solution for execution on the processors. We evaluate the proposed approach by comparing it with existing methods and generating the parallel code on a single-board computer with the big.LITTLE architecture to determine its effectiveness.

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Automatic Parallelization of Simulink Models for Multi-core Architectures

Cited by 10 publications

References 13 publications

Code Generation from Simulink Models with Task and Data Parallelism

Code Generation from Simulink Models with Task and Data Parallelism

Model-Based Parallelization for Simulink Models on Multicore CPUs and GPUs

Model-Based Parallelizer for Embedded Control Systems on Single-ISA Heterogeneous Multicore

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